US5591656A
Expired / Lapsed
US
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Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor
Assignee: Panasonic Holdings Corp
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Filing: 1995-05-30
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Granted: 1997-01-07
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Expires: 2015-05-30
Abstract
Abstract A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an IIL to be an injector are formed on a P-type silicon substrate 1 by self-aligned and integrated. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. In the epitaxial layer, the P-type intrinsic base layer of superhigh speed vertical NPN transistor is formed by impurity diffusion from the emitter leading-out electrode formed of polysilicon film, and the P-type base layer of the vertical NPN transistor having a reverse direction structure is formed by ion implantation. By thus forming the superhigh speed vertical NPN transistor having a reverse direction structure in self-aligned process, the superhigh speed vertical NPN transistor of self-aligned type and IIL device may be integrated on a same chip. Besides, by forming the intrinsic base layer of the vertical NPN transistor having a reverse direction structure deeper in junction than the base layer formed by impurity diffusion from the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type, the low concentration epitaxial layer part beneath the intrinsic base layer for composing the emitter of the vertical NPN transistor having a reverse direction structure may be made smaller, thereby avoiding lowering of the current gain of the vertical NPN transistor having a reverse direction structure and lowering of high speed operation of IIL device accompanying accumulation of minority carrier.
Inventors
- 👤 Shigeki Sawada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; Y; Y10; Y10S; Y10S148/00; Y10S148/01
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
271 words
A method of fabricating a semiconductor integrated circuit device which has a bipolar transistor and an IIL device produced by using a self-aligned method comprising the steps of: forming a semiconductor layer of a second conductive type on a semiconductor substrate of a first conductive type, wherein the semiconductor layer has at least a first and second semiconductor element region, said first semiconductor element region within said IIL device; forming a first diffusion layer of the first conductive type in the first semiconductor element region on the semiconductor layer; forming a first polycrystalline semiconductor film on the semiconductor substrate; forming a first insulating film on the first polycrystalline semiconductor film; introducing a first impurity of the first conductive type into the first polycrystalline semiconductor film; forming a first opening by selectively etching and removing the first insulating film and first polycrystalline semiconductor film; forming a second insulating film at least in the first opening; forming a second diffusion layer of the first conductive type by introducing the first impurity into the semiconductor layer; forming a second opening in the second insulating layer; growing a second polycrystalline semiconductor film in the second opening; introducing a second impurity of the first conductive type selectively into the second polycrystalline semiconductor film in the second semiconductor element region; forming a third diffusion layer by introducing the second impurity into the semiconductor layer through the second opening; introducing a third impurity of the second conductive type into the second polycrystalline semiconductor film; and forming a fourth diffusion layer of the second conductive type by introducing the third impurity into the semiconductor layer through the second opening.
Claim 2
Independent Claim
271 words
A method of fabricating a semiconductor integrated circuit device which has a bipolar transistor and an IIL device produced by using a self-aligned method comprising the steps of: forming a semiconductor layer of a second conductive type on a semiconductor substrate of a first conductive type, wherein the semiconductor layer has at least a first and second semiconductor element region, said first semiconductor element region within said IIL device; forming a first diffusion layer of the first conductive type in the first semiconductor element region on the semiconductor layer; forming a first polycrystalline semiconductor film on the semiconductor substrate; forming a first insulating film on the first polycrystalline semiconductor film; introducing a first impurity of the first conductive type into the first polycrystalline semiconductor film; forming a first opening by selectively etching and removing the first insulating film and first polycrystalline semiconductor film; forming a second insulating film at least in the first opening; forming a second diffusion layer of the first conductive type by introducing the first impurity into the semiconductor layer; forming a second opening in the second insulating layer; growing a second polycrystalline semiconductor film in the second opening; introducing a second impurity of the first conductive type selectively into the second polycrystalline semiconductor film in the second semiconductor element region; forming a third diffusion layer by introducing the second impurity into the semiconductor layer through the second opening; introducing a third impurity of the second conductive type into the second polycrystalline semiconductor film; and forming a fourth diffusion layer of the second conductive type by introducing the third impurity into the semiconductor layer through the second opening.
Claim 3
Independent Claim
290 words
A method of fabricating a semiconductor integrated circuit device which has a bipolar transistor and an IIL device produced by using a self-aligned method comprising the steps of: forming a semiconductor layer of a second conductive type on a semiconductor substrate of a first conductive type wherein the semiconductor layer has at least a first and second semiconductor element region, said first semiconductor element region within said IIL device; forming a first diffusion layer of the first conductive type in the first semiconductor element region of the semiconductor layer; forming a first polycrystalline semiconductor film on the semiconductor substrate; forming a first insulating film on the first polycrystalline semiconductor film; introducing a first impurity of the first conductive type in the first polycrystalline semiconductor film; forming a first opening by selectively etching and removing the first insulating film and first polycrystalline semiconductor film; forming a second insulating film at least within the first opening; forming a second diffusion layer of the first conductive type by introducing the first impurity into the semiconductor layer; forming a second polycrystalline semiconductor element film on the second insulating film; forming a second opening in the second insulating film and second polycrystalline semiconductor film; growing a third polycrystalline semiconductor film at least within the second opening; introducing a second impurity of the first conductive type selectively in the third polycrystalline semiconductor film of the second semiconductor element region; forming a third diffusion layer by introducing the second impurity into the semiconductor layer through the second opening; introducing a third impurity of the second conductive type into the third polycrystalline semiconductor film; and forming a fourth diffusion layer of the second conductive type by introducing the third impurity into the semiconductor layer through the second opening.
Claim 4
Independent Claim
290 words
A method of fabricating a semiconductor integrated circuit device which has a bipolar transistor and an IIL device produced by using a self-aligned method comprising the steps of: forming a semiconductor layer of a second conductive type on a semiconductor substrate of a first conductive type wherein the semiconductor layer has at least a first and second semiconductor element region, said first semiconductor element region within said IIL device; forming a first diffusion layer of the first conductive type in the first semiconductor element region of the semiconductor layer; forming a first polycrystalline semiconductor film on the semiconductor substrate; forming a first insulating film on the first polycrystalline semiconductor film; introducing a first impurity of the first conductive type in the first polycrystalline semiconductor film; forming a first opening by selectively etching and removing the first insulating film and first polycrystalline semiconductor film; forming a second insulating film at least within the first opening; forming a second diffusion layer of the first conductive type by introducing the first impurity into the semiconductor layer; forming a second polycrystalline semiconductor element film on the second insulating film; forming a second opening in the second insulating film and second polycrystalline semiconductor film; growing a third polycrystalline semiconductor film at least within the second opening; introducing a second impurity of the first conductive type selectively in the third polycrystalline semiconductor film of the second semiconductor element region; forming a third diffusion layer by introducing the second impurity into the semiconductor layer through the second opening; introducing a third impurity of the second conductive type into the third polycrystalline semiconductor film; and forming a fourth diffusion layer of the second conductive type by introducing the third impurity into the semiconductor layer through the second opening.
References Cited (Backward Citations)
US3912555A
Cited
JPS56150850A
Cited
JPS5821366A
Cited
US4826780A
Cited
EP0193934A2
Cited
EP0250869A1
Cited
JPS6343357A
Cited
US5014107A
Cited
US5072287A
Cited
DE3915634A1
Cited
JPH0319278A
Cited
US5162252A
Cited
JP3019278U
Cited
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