US5162252A
Expired / Lapsed
US
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Method of fabricating iil and vertical complementary bipolar transistors
Assignee: Panasonic Holdings Corp
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Filing: 1991-12-17
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Granted: 1992-11-10
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Expires: 2011-12-17
Abstract
Abstract The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n + -type first buried layer (5), a p + -type second buried layer (8) having a lower impurity density than the n + -type first buried layer (5), and at least one of n + -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.
Inventors
- 👤 Akihiro Kanda
- 👤 Mitsuo Tanaka
- 👤 Takehiro Hirai
- 👤 Masahiro Nakatani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10D84/01; H10D84/0112; H10D84/0116; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S148/00; Y10S148/087
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
229 words
A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of; forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer; forming in said first buried layer a one-conductivity type second buried layer; forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type semiconductor layer; forming in said semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer; forming in said first diffused layer a reverse-conductivity type second diffused layer in singularity or plurality; and forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer; said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, and said third diffused layer as an injector of the IIL; said second diffused layer being so formed as to come into contact with said second buried layer; the impurity density of the base right beneath the collector being lower than the impurity density of the emitter; and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.
Claim 2
Independent Claim
229 words
A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of; forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer; forming in said first buried layer a one-conductivity type second buried layer; forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type semiconductor layer; forming in said semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer; forming in said first diffused layer a reverse-conductivity type second diffused layer in singularity or plurality; and forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer; said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, and said third diffused layer as an injector of the IIL; said second diffused layer being so formed as to come into contact with said second buried layer; the impurity density of the base right beneath the collector being lower than the impurity density of the emitter; and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.
Claim 3
Dependent Claim
146 words
A method of fabricating a semiconductor device according to claim 1, wherein; a collector buried layer in the vertical npn transistor is formed at the same time as the formation of said first buried layer; a lower separating region in the device separating region and a collector buried layer in the vertical pnp transistor are formed at the same time as the formation of said second buried layer; an upper separating region in the device separating region and a collector region in the vertical pnp transistor are formed at the same time as the formation of said first diffused layer; a collector wall region in the vertical npn transistor is formed at the same time as the formation of said second diffused layer; and a base region in the vertical npn transistor is formed at the same time as the formation of said third diffused layer.
Claim 4
Independent Claim
315 words
A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of; forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer; forming in said first buried layer a one-conductivity type second buried layer; forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type first semiconductor layer; forming in said first semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer; forming in said first diffused layer a reverse-conductivity type second diffused layer coming into contact with said second buried layer, formed in singularity or plurality; forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer; forming in said first semiconductor layer a groove that reaches said first buried layer, so formed as to surround the sides of said first diffused layer and said third diffused layer on their sides other than their sides opposed to each other; forming an insulating film only on each side wall of said groove; and filling said groove with a reverse-conductivity type second semiconductor layer so as to be connected with said first buried layer at the bottom of said groove; said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, said third diffused layer as an injector of the IIL, and said second semiconductor layer as an emitter lead-out electrode of the IIL; the impurity density of the base right beneath the collector being lower than the impurity density of the emitter; and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.
Claim 5
Independent Claim
315 words
A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of; forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer; forming in said first buried layer a one-conductivity type second buried layer; forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type first semiconductor layer; forming in said first semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer; forming in said first diffused layer a reverse-conductivity type second diffused layer coming into contact with said second buried layer, formed in singularity or plurality; forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer; forming in said first semiconductor layer a groove that reaches said first buried layer, so formed as to surround the sides of said first diffused layer and said third diffused layer on their sides other than their sides opposed to each other; forming an insulating film only on each side wall of said groove; and filling said groove with a reverse-conductivity type second semiconductor layer so as to be connected with said first buried layer at the bottom of said groove; said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, said third diffused layer as an injector of the IIL, and said second semiconductor layer as an emitter lead-out electrode of the IIL; the impurity density of the base right beneath the collector being lower than the impurity density of the emitter; and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.
Claim 6
Dependent Claim
170 words
A method of fabricating a semiconductor device according to claim 3, wherein; a collector buried layer in the vertical npn transistor is formed at the same time as the formation of said first buried layer; a lower separating region in the device separating region and a collector buried layer in the vertical pnp transistor are formed at the same time as the formation of said second buried layer; an upper separating region in the device separating region and a collector region in the vertical pnp transistor are formed at the same time as the formation of said first diffused layer; a base region in the vertical npn transistor is formed at the same time as the formation of said third diffused layer; and a groove serving as a collector lead-out electrode in the vertical npn transistor, having an insulating film on each side wall thereof and filled therein with another second semiconductor layer is formed at the same time as the formation of the emitter lead-out electrode of the IIL.
Claim 7
Independent Claim
279 words
A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of; forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer; forming in said first buried layer a one-conductivity type second buried layer; forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type first semiconductor layer; forming in said first semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer; forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer; forming in said first diffused layer a groove that substantially reaches said second buried layer, formed in singularity or plurality; forming an insulating film only on each side wall of said groove; filling said groove with a reverse-conductivity type second semiconductor; and forming a reverse-conductivity type second diffused layer coming into contact with said second buried layer, by causing a reverse-conductivity type impurity to diffuse from said second semiconductor layer; said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, said third diffused layer as an injector of the IIL, and said second semiconductor layer as a collector lead-out electrode of the IIL; the impurity density of the base right beneath the collector being lower than the impurity density of the emitter; and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.
Claim 8
Independent Claim
279 words
A method of fabricating a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL, comprising the steps of; forming in a one-conductivity type semiconductor substrate a reverse-conductivity type first buried layer; forming in said first buried layer a one-conductivity type second buried layer; forming on said semiconductor substrate having said first and second buried layers a reverse-conductivity type first semiconductor layer; forming in said first semiconductor layer a one-conductivity type first diffused layer coming into contact with said second buried layer; forming a one-conductivity type third diffused layer at a position set apart in the lateral direction with respect to said first diffused layer; forming in said first diffused layer a groove that substantially reaches said second buried layer, formed in singularity or plurality; forming an insulating film only on each side wall of said groove; filling said groove with a reverse-conductivity type second semiconductor; and forming a reverse-conductivity type second diffused layer coming into contact with said second buried layer, by causing a reverse-conductivity type impurity to diffuse from said second semiconductor layer; said first buried layer being made to serve as an emitter of the IIL, said second buried layer and said first diffused layer as the base of the IIL, said second diffused layer as a collector of the IIL, said third diffused layer as an injector of the IIL, and said second semiconductor layer as a collector lead-out electrode of the IIL; the impurity density of the base right beneath the collector being lower than the impurity density of the emitter; and the impurity density of the base being made to monotonously become lower from the emitter toward the collector.
Claim 9
Dependent Claim
123 words
A method of fabricating a semiconductor device according to claim 5, wherein; a collector buried layer in the vertical npn transistor is formed at the same time as the formation of said first buried layer; a lower separating region in the device separating region and a collector buried layer in the vertical pnp transistor are formed at the same time as the formation of said second buried layer; an upper separating region in the device separating region and a collector region in the vertical pnp transistor are formed at the same time as the formation of said first diffused layer; and a base region in the vertical npn transistor is formed at the same time as the formation of said third diffused layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |