Method of manufacturing flash memory with inclined channel region

Claim 1

A method for forming a electrically erasable and programmable memory comprising the steps of: forming a device isolation oxide film on a region of a main surface of a semiconductor substrate of a first conductivity type, the region being where a device isolation region is to be formed and a portion of an active region is to be formed; removing an oxide film including part of the device isolation oxide film to form the portion of the active region, the portion of the active region having an inclined portion on a surface thereof; forming a first gate insulating film on the inclined portion of the active region and a second gate insulating film on the active region except for the inclined portion; forming a floating gate electrode on the first gate insulating film; forming a third gate insulating film on the floating gate electrode; forming a control gate electrode so that the control gate electrode is patterned in such a manner that the control gate at least partially overlies the floating gate electrode; implanting impurity ions of a second conductivity type using the floating gate electrode as a mask thereby forming either a source region or a drain region where at least some of the device isolation oxide film has been removed.

Claim 2

A method for forming a electrically erasable and programmable memory comprising the steps of: forming a device isolation oxide film on a region of a main surface of a semiconductor substrate of a first conductivity type, the region being where a device isolation region is to be formed and a portion of an active region is to be formed; removing an oxide film including part of the device isolation oxide film to form the portion of the active region, the portion of the active region having an inclined portion on a surface thereof; forming a first gate insulating film on the inclined portion of the active region and a second gate insulating film on the active region except for the inclined portion; forming a floating gate electrode on the first gate insulating film; forming a third gate insulating film on the floating gate electrode; forming a control gate electrode so that the control gate electrode is patterned in such a manner that the control gate at least partially overlies the floating gate electrode; implanting impurity ions of a second conductivity type using the floating gate electrode as a mask thereby forming either a source region or a drain region where at least some of the device isolation oxide film has been removed.

Claim 7

A method for forming a electrically erasable and programmable memory, the method comprising the steps of: preparing a source region and a drain region in spaced-apart relation on a main surface of a semiconductor substrate; providing a channel region between the source region and the drain region, at least a portion of the channel region being inclined so that the source region and the drain region are not vertically coextensive; providing a gate insulating first film on the channel region; forming a floating gate electrode on the gate insulating first film; using the floating gate electrode as a mask for implanting impurity ions into at least one of the source region and the drain region.

Claim 8

A method for forming a electrically erasable and programmable memory, the method comprising the steps of: preparing a source region and a drain region in spaced-apart relation on a main surface of a semiconductor substrate; providing a channel region between the source region and the drain region, at least a portion of the channel region being inclined so that the source region and the drain region are not vertically coextensive; providing a gate insulating first film on the channel region; forming a floating gate electrode on the gate insulating first film; using the floating gate electrode as a mask for implanting impurity ions into at least one of the source region and the drain region.