Multi-surfaced capacitor for storing more charge per horizontal chip area

Claim 2

A semiconductor chip comprising: a semiconductor substrate, first and second regions of a first conductivity type deposed therein, said regions being separated by a third region of a second conductivity type; a first elongated dielectric layer disposed on a portion of a surface of said substrate overlying a portion of said third region; a first, conductive, elongated capacitor plate, having a selected width and further having a pair of sidewalls of a selected height, located over said first dielectric layer on said substrate and separated from said third region in said substrate by said first dielectric layer, a second dielectric layer deposed along substantially the full length of a first one of said pair of sidewalls; a third dielectric layer deposed along substantially the full length of the other one of said pair of sidewalls; a fourth dielectric layer disposed over substantially the full length of said top surface; and a second capacitor conductive plate extending along substantially the full length of one of the dielectric layers on one of said sidewalls and in electrical contact with said first region in said substrate, wherein the first capacitor plate has a top surface that is non-planar.

Claim 3

A semiconductor chip comprising: a semiconductor substrate, first and second regions of a first conductivity type deposed therein, said regions being separated by a third region of a second conductivity type; a first elongated dielectric layer disposed on a portion of a surface of said substrate overlying a portion of said third region; a first, conductive, elongated capacitor plate, having a selected width and further having a pair of sidewalls of a selected height, located over said first dielectric layer on said substrate and separated from said third region in said substrate by said first dielectric layer, a second dielectric layer deposed along substantially the full length of a first one of said pair of sidewalls; a third dielectric layer deposed along substantially the full length of the other one of said pair of sidewalls; a fourth dielectric layer disposed over substantially the full length of said top surface; and a second capacitor conductive plate extending along substantially the full length of one of the dielectric layers on one of said sidewalls and in electrical contact with said first region in said substrate, wherein said first plate is coupled to an external power supply input, and said second plate is coupled to an internal power supply, wherein the first capacitor plate has a top surface that is non-planar.

Claim 4

A semiconductor chip comprising: a semiconductor substrate, first and second regions of a first conductivity type deposed therein, said regions being separated by a third region of a second conductivity type; a first elongated dielectric layer disposed on a portion of a surface of said substrate overlying a portion of said third region; a first, conductive, elongated capacitor plate, having a selected width and further having a pair of sidewalls of a selected height, located over said first dielectric layer on said substrate and separated from said third region in said substrate by said first dielectric layer, a second dielectric layer deposed along substantially the full length of a first one of said pair of sidewalls; a third dielectric layer deposed along substantially the full length of the other one of said pair of sidewalls; a fourth dielectric layer disposed over substantially the full length of said top surface; and a second capacitor conductive plate extending along substantially the full length of one of the dielectric layers on one of said sidewalls and in electrical contact with said first region in said substrate, wherein said first plate is coupled to an external power supply input, and said second plate is coupled to an internal power supply, wherein the first capacitor plate has a top surface that is non-planar.