Patent US5587954A successfully refreshed from Google Patents.
US5587954A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
Assignee: Texas Instruments Inc
•
Filing: 1994-10-21
•
Granted: 1996-12-24
•
Expires: 2014-10-21
Abstract
Abstract A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
Inventors
- 👤 Wilbur C. Vogley
- 👤 Anthony M. Balistreri
- 👤 Karl M. Guttag
- 👤 Steven D. Krueger
- 👤 Duy-Loan T. Le
- 👤 Joseph H. Neal
- 👤 Kenneth A. Poteet
- 👤 Joseph P. Hartigan
- 👤 Roger D. Norwood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/1015; G11C7/1018; G11C7/1072
Claims Analysis
Total Claims: 63
Claim 1
Independent Claim
92 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having timing edges for controlling operation of the digital processor; a synchronous random access memory, directly responsive to the edges of the system clock signal, for accessing addressable storage cells within the synchronous memory to write data into the storage cells and to read out data from the storage cells; and the synchronous random access memory including input and output data latches arranged for latching data directly in response to the system clock signal.
Claim 2
Dependent Claim
92 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having timing edges for controlling operation of the digital processor; a synchronous random access memory, directly responsive to the edges of the system clock signal, for accessing addressable storage cells within the synchronous memory to write data into the storage cells and to read out data from the storage cells; and the synchronous random access memory including input and output data latches arranged for latching data directly in response to the system clock signal.
Claim 3
Dependent Claim
125 words
A data processing system, in accordance with claim 1, further comprising a timing and control circuit, directly responsive to the edges of the system clock signal, for producing control signals synchronized with the system clock signal to control write-in and read out operations of the synchronous random access memory; row address circuitry, responsive to a first control signal produced by the control and timing circuit, for accessing a row of addressable storage cells to write data in or to read data out of the synchronous memory; and column address circuitry, responsive to other control signals produced by the control and timing circuit, for accessing a block of columns of addressable storage cells to write data in or to read data out of the synchronous memory.
Claim 4
Dependent Claim
30 words
A data processing system, in accordance with claim 1, wherein the synchronous random access memory is fabricated as a metal oxide semiconductor device having an array of static storage cells.
Claim 5
Dependent Claim
30 words
A data processing system, in accordance with claim 1, wherein the synchronous random access memory is fabricated as a metal oxide semiconductor device having an array of dynamic storage cells.
Claim 6
Dependent Claim
41 words
A data processing system, in accordance with claim 1, wherein the digital processor produces control signals that are applied to a timing and control circuit together with the system clock signal for controlling generation of synchronous random access memory control signals.
Claim 7
Dependent Claim
24 words
A data processing system, in accordance with claim 5, wherein the array of dynamic storage cells is fabricated as complementary metal oxide semiconductor circuits.
Claim 8
Dependent Claim
25 words
A data processing system, in accordance with claim 5, wherein the array of dynamic storage cells is fabricated as bipolar complementary metal oxide semiconductor circuits.
Claim 9
Dependent Claim
115 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having a timing edge for controlling operation of the digital processor; a synchronous random access memory arranged for storing data in an array of storage cells, which are addressable by row and column addresses; the digital processor being responsive to edges of the system clock signal and arranged for producing a gated system clock signal having timing edges correlated with the timing edges of the system clock signal; and the synchronous random access memory being directly responsive to the edges of the gated system clock signal for accessing the storage cells for write-in and read out operations.
Claim 10
Dependent Claim
115 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having a timing edge for controlling operation of the digital processor; a synchronous random access memory arranged for storing data in an array of storage cells, which are addressable by row and column addresses; the digital processor being responsive to edges of the system clock signal and arranged for producing a gated system clock signal having timing edges correlated with the timing edges of the system clock signal; and the synchronous random access memory being directly responsive to the edges of the gated system clock signal for accessing the storage cells for write-in and read out operations.
Claim 11
Dependent Claim
89 words
A synchronous random access memory comprising: an array of storage cells arranged in addressable rows and columns; a row address buffer; a row address decoder; a column address buffer; a column address decoder; and circuitry, responsive to edges of a system clock signal applied directly from a microprocessor, for enabling row address data to be stored in the row address buffer for decoding through the row address decoder and for enabling column address data to be stored in the column address buffer for decoding in the column address decoder.
Claim 12
Dependent Claim
89 words
A synchronous random access memory comprising: an array of storage cells arranged in addressable rows and columns; a row address buffer; a row address decoder; a column address buffer; a column address decoder; and circuitry, responsive to edges of a system clock signal applied directly from a microprocessor, for enabling row address data to be stored in the row address buffer for decoding through the row address decoder and for enabling column address data to be stored in the column address buffer for decoding in the column address decoder.
Claim 13
Dependent Claim
159 words
A synchronous random access memory, in accordance with claim 9, wherein a row address control signal, in conjunction with an edge of the system clock signal, enables the row address buffer to store the row address data; a column address control signal, in conjunction with an edge of the system clock signal, enables the column address buffer to store the column address data; a write signal, in conjunction with an edge of the system clock signal, generates a write control signal that enables data, applied to an input terminal of the synchronous random access memory, to be written into an addressed storage cell in synchronism with the system clock signal; and a read signal, in conjunction with an edge of the system clock signal, generates a read control signal that enables data, stored in an addressed storage cell, to be read out to an output terminal of the synchronous random access memory in synchronism with the system clock signal.
Claim 14
Dependent Claim
84 words
A synchronous random access memory comprising: an array of storage cells arranged in addressable rows and columns; a row address buffer; a row address decoder; a column address buffer; a column address decoder; and circuitry, responsive to edges of a system clock signal, for enabling row address data to be stored in the row address buffer for decoding through the row address decoder and for enabling column address data to be stored in the column address buffer for decoding in the column address decoder.
Claim 15
Dependent Claim
84 words
A synchronous random access memory comprising: an array of storage cells arranged in addressable rows and columns; a row address buffer; a row address decoder; a column address buffer; a column address decoder; and circuitry, responsive to edges of a system clock signal, for enabling row address data to be stored in the row address buffer for decoding through the row address decoder and for enabling column address data to be stored in the column address buffer for decoding in the column address decoder.
Claim 16
Dependent Claim
145 words
A synchronous random access memory, in accordance with claim 11, wherein a row address control signal, in conjunction with an edge of the system clock signal, enables the row address buffer to store the row address data; a column address control signal, in conjunction with an edge of the system clock signal, enables the column address buffer to store the column address data; a write signal, in conjunction with an edge of the system clock signal, generates a write control signal that enables data, applied to an input terminal of the synchronous random access memory, to be written into an addressed storage cell; and a read signal, in conjunction with an edge of the system clock signal, generates a read control signal that enables data, stored in an addressed storage cell, to be read out to an output terminal of the synchronous random access memory.
Claim 17
Dependent Claim
109 words
A synchronous random access memory, in accordance with claim 11, further comprising a column address counter, interposed between the column address buffer and the column address decoder, for receiving an initial column address; the column address decoder, in response to a most significant group of bits in the column address counter, accesses a block of columns of storage cells in the array for writing in data or for reading out data; and an input or output multiplexer, responsive to a least significant group of bits in the column address counter, establishes a conduction path for data bits being written into or read out of the array of storage cells.
Claim 18
Dependent Claim
40 words
A synchronous random access memory in accordance with claim 11, wherein a circuit for receiving a write signal that controls the synchronous random access memory to selectively write or read data in concurrence with edges of the system clock signal.
Claim 19
Dependent Claim
38 words
A synchronous random access memory in accordance with claim 11, wherein in response to edges of the system clock signal, the synchronous random access memory performs a random access read operation in synchronism with the system clock signal.
Claim 20
Dependent Claim
38 words
A synchronous random access memory, in accordance with claim 11, wherein in response to edges of the system clock signal, the synchronous random access memory performs a random access write operation in synchronism with the system clock signal.
Claim 21
Dependent Claim
43 words
A synchronous random access memory, in accordance with claim 11, wherein in response to edges of the system clock signal, a read signal, a burst select signal, and a burst increment signal, the synchronous random access memory performs a synchronous burst read-up operation.
Claim 22
Dependent Claim
43 words
A synchronous random access memory, in accordance with claim 11, wherein in response to edges of the system clock signal, a read signal, a burst select signal, and a burst decrement signal, the synchronous random access memory performs a synchronous burst read-down operation.
Claim 23
Dependent Claim
43 words
A synchronous random access memory, in accordance with claim 11, wherein in response to edges of the system clock signal, a write signal, a burst select signal, and a burst increment signal, the synchronous random access memory performs a synchronous burst write-up operation.
Claim 24
Dependent Claim
42 words
A synchronous random access memory, in accordance with claim 11, wherein in response to edges of the system clock signal, a write signal, a burst signal, and a burst decrement signal, the synchronous random access memory performs a synchronous burst write-down operation.
Claim 25
Dependent Claim
25 words
A synchronous random access memory, in accordance with claim 11, wherein the array of storage cells is fabricated as an array of static memory circuits.
Claim 26
Dependent Claim
24 words
A synchronous random access memory, in accordance with claim 21, wherein the array of storage cells is fabricated as a metal oxide semiconductor device.
Claim 27
Dependent Claim
22 words
A synchronous random access memory, in accordance with claim 22, wherein the array of storage cells comprises complementary metal oxide semiconductor circuits.
Claim 28
Dependent Claim
23 words
A synchronous random access memory, in accordance with claim 22, wherein the array of storage cells comprises bipolar complementary metal oxide semiconductor circuits.
Claim 29
Dependent Claim
25 words
A synchronous random access memory, in accordance with claim 11, wherein the array of storage cells is fabricated as an array of dynamic memory circuits.
Claim 30
Dependent Claim
24 words
A synchronous random access memory, in accordance with claim 25, wherein the array of storage cells is fabricated as a metal oxide semiconductor device.
Claim 31
Dependent Claim
22 words
A synchronous random access memory in accordance with claim 26, wherein the array of storage cells comprises complementary metal oxide semiconductor circuits.
Claim 32
Dependent Claim
23 words
A synchronous random access memory in accordance with claim 26, wherein the array of storage cells comprises bipolar complementary metal oxide semiconductor circuits.
Claim 33
Dependent Claim
47 words
A synchronous random access memory, in accordance with claim 11, wherein in response to edges of the system clock signal, a read signal, a burst select signal, a wrap length signal, and a wrap control signal, the synchronous random access memory performs a synchronous wrap read operation.
Claim 34
Dependent Claim
47 words
A synchronous random access memory, in accordance with claim 11, wherein in response to edges of the system clock signal, a write signal, a burst select signal, a wrap length signal and a wrap control signal, the synchronous random access memory performs a synchronous wrap write operation.
Claim 35
Dependent Claim
34 words
A data processing system, in accordance with claim 1, wherein the timing edges are rising edges; and the input and output latches are arranged for latching data in direct response to the rising edges.
Claim 36
Dependent Claim
34 words
A data processing system, in accordance with claim 1, wherein the timing edges are falling edges; and the input and output latches are arranged for latching data directly in response to the falling edges.
Claim 37
Dependent Claim
41 words
A data processing system, in accordance with claim 1, wherein the timing edges are rising and falling edges; and the input and output latches are arranged for latching data directly in response either to the rising edges or the falling edges.
Claim 38
Dependent Claim
38 words
A data processing system, in accordance with claim 2, wherein the edges of the system clock signal are rising edges; and the input and output latches are arranged for latching data directly in response to the rising edges.
Claim 39
Dependent Claim
38 words
A data processing system, in accordance with claim 2, wherein the edges of the system clock signal are falling edges; and the input and output latches are arranged for latching data directly in response to the falling edges.
Claim 40
Dependent Claim
44 words
A data processing system, in accordance with claim 2, wherein the edges of the system clock signal are rising and falling edges; and the input and output latches are arranged for latching data directly in response either to the rising or the falling edges.
Claim 41
Dependent Claim
205 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having timing edges for controlling operation of the digital processor; a synchronous random access memory, directly responsive to the edges of the system clock signal, for accessing addressable storage cells within the synchronous memory to write data into the storage cells and to read out data from the storage cells; the synchronous random access memory including input and output data latches arranged for latching data directly in response to the system clock signal; a timing and control circuit, directly responsive to the edges of the system clock signal, for producing control signals synchronized with the system clock signal to control write-in and read out operations of the synchronous random access memory; row address circuitry, responsive to a first control signal produced by the control and timing circuit, for accessing a row of addressable storage cells to write data in or to read data out of the synchronous memory; and column address circuitry, responsive to other control signals produced by the control and timing circuit, for accessing a set of columns of addressable storage cells to write data in or to read data out of the synchronous memory.
Claim 42
Dependent Claim
205 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having timing edges for controlling operation of the digital processor; a synchronous random access memory, directly responsive to the edges of the system clock signal, for accessing addressable storage cells within the synchronous memory to write data into the storage cells and to read out data from the storage cells; the synchronous random access memory including input and output data latches arranged for latching data directly in response to the system clock signal; a timing and control circuit, directly responsive to the edges of the system clock signal, for producing control signals synchronized with the system clock signal to control write-in and read out operations of the synchronous random access memory; row address circuitry, responsive to a first control signal produced by the control and timing circuit, for accessing a row of addressable storage cells to write data in or to read data out of the synchronous memory; and column address circuitry, responsive to other control signals produced by the control and timing circuit, for accessing a set of columns of addressable storage cells to write data in or to read data out of the synchronous memory.
Claim 43
Dependent Claim
21 words
A data processing system, in accordance with claim 37, wherein the timing edges of the system clock signal are positive-going edges.
Claim 44
Dependent Claim
21 words
A data processing system, in accordance with claim 37, wherein the timing edges of the system clock signal are negative-going edges.
Claim 45
Dependent Claim
18 words
A data processing system, in accordance with claim 37, wherein the timing edges are positive-going or negative-going edges.
Claim 46
Dependent Claim
128 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having either rising or falling timing edges for controlling operation of the digital processor; a synchronous random access memory arranged for storing data in an array of storage cells, which are addressable by row and column addresses; the digital processor being responsive to the timing edges of the system clock signal and arranged for producing a gated system clock signal having either rising or falling timing edges correlated with the timing edges of the system clock signal; and the synchronous random access memory being directly responsive either to the rising or falling edges of the gated system clock signal for accessing the storage cells for write-in and read out operations.
Claim 47
Dependent Claim
128 words
A data processing system comprising a digital processor; a system clock circuit for producing a system clock signal having either rising or falling timing edges for controlling operation of the digital processor; a synchronous random access memory arranged for storing data in an array of storage cells, which are addressable by row and column addresses; the digital processor being responsive to the timing edges of the system clock signal and arranged for producing a gated system clock signal having either rising or falling timing edges correlated with the timing edges of the system clock signal; and the synchronous random access memory being directly responsive either to the rising or falling edges of the gated system clock signal for accessing the storage cells for write-in and read out operations.
Claim 48
Dependent Claim
47 words
A synchronous random access memory comprising: an array of addressable storage cells; a circuit for receiving a system clock signal; and circuitry, responsive to edges of the system clock signal, for enabling address data to be stored in an address circuit for decoding through an address decoder.
Claim 49
Dependent Claim
47 words
A synchronous random access memory comprising: an array of addressable storage cells; a circuit for receiving a system clock signal; and circuitry, responsive to edges of the system clock signal, for enabling address data to be stored in an address circuit for decoding through an address decoder.
Claim 50
Dependent Claim
16 words
A synchronous random access memory, in accordance with claim 42, wherein the edges are positive-going edges.
Claim 51
Dependent Claim
16 words
A synchronous random access memory, in accordance with claim 42, wherein the edges are negative-going edges.
Claim 52
Dependent Claim
19 words
A synchronous random access memory, in accordance with claim 42, wherein the edges are either negative-going or positive-going edges.
Claim 53
Dependent Claim
167 words
A synchronous random access memory, in accordance with claim 42, wherein a row address control signal, in conjunction with an edge of the system clock signal, enables a row address part of the address circuit to store the row address data; a column address control signal, in conjunction with an edge of the system clock signal, enables a column address part of the address circuit to store the column address data; a write signal, in conjunction with an edge of the system clock signal, generates a write control signal that enables data, applied to an input terminal of the synchronous random access memory, to be written into an addressed storage cell in synchronism with the system clock signal; and a read signal, in conjunction with an edge of the system clock signal, generates a read control signal that enables data, stored in an addressed storage cell, to be read out to an output terminal of the synchronous random access memory in synchronism with the system clock signal.
Claim 54
Dependent Claim
19 words
A synchronous random access memory, in accordance with claim 46, wherein the edges are either negative-going or positive-going edges.
Claim 55
Dependent Claim
48 words
A synchronous random access memory comprising: an array of addressable storage cells; a circuit for receiving a system clock signal; and circuitry, responsive to an edge of the system clock signal, for enabling address data to be stored in an address buffer for decoding through an address decoder.
Claim 56
Dependent Claim
48 words
A synchronous random access memory comprising: an array of addressable storage cells; a circuit for receiving a system clock signal; and circuitry, responsive to an edge of the system clock signal, for enabling address data to be stored in an address buffer for decoding through an address decoder.
Claim 57
Dependent Claim
22 words
A synchronous random access memory, in accordance with claim 48, wherein the edge is either a negative-going transition or a positive-going transition.
Claim 58
Dependent Claim
167 words
A synchronous random access memory, in accordance with claim 48, wherein a row address control signal, in conjunction with the edge of the system clock signal, enables a row address part of the address circuit to store the row address data; a column address control signal, in conjunction with the edge of the system clock signal, enables a column address part of the address circuit to store the column address data; a write signal, in conjunction with the edge of the system clock signal, generates a write control signal that enables data, applied to an input terminal of the synchronous random access memory, to be written into an addressed storage cell in synchronism with the system clock signal; and a read signal, in conjunction with the edge of the system clock signal, generates a read control signal that enables data, stored in an addressed storage cell, to be read out to an output terminal of the synchronous random access memory in synchronism with the system clock signal.
Claim 59
Dependent Claim
22 words
A synchronous random access memory, in accordance with claim 50, wherein the edge is either a negative-going transition or a positive-going transition.
Claim 60
Dependent Claim
100 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a system clock circuit, producing a system clock signal having timing edges, for controlling operation of the digital processor, the input peripheral device, and the output peripheral device; and a synchronous dynamic random access memory, directly responsive to the timing edges of the system clock signal, for accessing addressable storage cells within the synchronous dynamic random access memory to write data into the storage cells and to read out data from the storage cells.
Claim 61
Dependent Claim
100 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a system clock circuit, producing a system clock signal having timing edges, for controlling operation of the digital processor, the input peripheral device, and the output peripheral device; and a synchronous dynamic random access memory, directly responsive to the timing edges of the system clock signal, for accessing addressable storage cells within the synchronous dynamic random access memory to write data into the storage cells and to read out data from the storage cells.
Claim 62
Dependent Claim
109 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a clock circuit, producing a clock signal for controlling operation of the digital processor, the digital processor producing a system clock signal having timing edges for controlling operation of the input peripheral device and the output peripheral device; and a synchronous random access memory, directly responsive to the timing edges of the system clock signal, for accessing addressable storage cells within the synchronous dynamic random access memory to write data into the storage cells and to read out data from the storage cells.
Claim 63
Dependent Claim
109 words
A data processing system comprising: a digital processor; an input peripheral device interconnected with the digital processor; an output peripheral device interconnected with the digital processor; a clock circuit, producing a clock signal for controlling operation of the digital processor, the digital processor producing a system clock signal having timing edges for controlling operation of the input peripheral device and the output peripheral device; and a synchronous random access memory, directly responsive to the timing edges of the system clock signal, for accessing addressable storage cells within the synchronous dynamic random access memory to write data into the storage cells and to read out data from the storage cells.
References Cited (Backward Citations)
JPS5956276A
Cited
US4649511A
Cited
US4618947A
Cited
US4618947B1
Cited
US4999814A
Cited
US5093807A
Cited
US5179670A
Cited
US5226011A
Cited
US5243703A
Cited
US5077693A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |