US5586295A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Combination prefetch buffer and instruction cache
Assignee: GlobalFoundries Inc
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Filing: 1995-06-05
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Granted: 1996-12-17
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Expires: 2015-06-05
Abstract
Abstract A cache memory system features a combination instruction cache and prefetch buffer, which obviates any requirement for a bus interconnecting the cache and buffer and which also effectively allows the instruction buffer to write data into the cache with improved utilization of prefetched instructions and with decreased use of power and silicon space.
Inventors
- 👤 Thang Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F9/3808; G06F2212/00; G06F2212/60; G06F2212/6022; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
100 words
A combination prefetch buffer and instruction cache comprising: an instruction cache portion having a plurality of blocks; a prefetch buffer portion having a plurality of words, wherein quantity of the plurality of words equals quantity of the plurality of blocks; a first set of validity bits that indicate validity of instruction words stored in the prefetch buffer; and a second set of validity bits that indicate whether the instruction words have been updated in the instruction cache portion, such that writing the instruction words in the instruction cache portion and sending the instruction words to a decoder are independent operations.
Claim 2
Dependent Claim
100 words
A combination prefetch buffer and instruction cache comprising: an instruction cache portion having a plurality of blocks; a prefetch buffer portion having a plurality of words, wherein quantity of the plurality of words equals quantity of the plurality of blocks; a first set of validity bits that indicate validity of instruction words stored in the prefetch buffer; and a second set of validity bits that indicate whether the instruction words have been updated in the instruction cache portion, such that writing the instruction words in the instruction cache portion and sending the instruction words to a decoder are independent operations.
Claim 3
Dependent Claim
23 words
The combination prefetch buffer and instruction cache of claim 1, wherein said prefetch buffer portion comprises a write counter and a read counter.
Claim 4
Dependent Claim
36 words
The combination prefetch buffer and instruction cache of claim 2, wherein said prefetch buffer portion is configured to operate in a first-in, first-out manner, which configuration inherently defines a head portion and a tail portion thereof.
Claim 5
Independent Claim
149 words
A method for providing instruction words to a central processing unit utilizing combination prefetch buffer and instruction cache, the method comprising the steps of; a) when required instructions are not in an instruction cache portion, fetching the required instructions from an external memory; b) storing, by a prefetch buffer portion of the combination prefetch buffer and instruction cache, the required instructions received from the external memory; c) setting a first set of bits to indicate that the required instructions stored in the prefetch buffer portion are valid; d) sending, by the prefetch buffer portion, the required instructions to the instruction cache portion and the central processing unit; e) setting a second set of bits when the required instructions are updated in the instruction cache portion, such that writing the required instructions into the instruction cache portion and providing the required instructions to the central processing unit are independent operations.
Claim 6
Independent Claim
149 words
A method for providing instruction words to a central processing unit utilizing combination prefetch buffer and instruction cache, the method comprising the steps of; a) when required instructions are not in an instruction cache portion, fetching the required instructions from an external memory; b) storing, by a prefetch buffer portion of the combination prefetch buffer and instruction cache, the required instructions received from the external memory; c) setting a first set of bits to indicate that the required instructions stored in the prefetch buffer portion are valid; d) sending, by the prefetch buffer portion, the required instructions to the instruction cache portion and the central processing unit; e) setting a second set of bits when the required instructions are updated in the instruction cache portion, such that writing the required instructions into the instruction cache portion and providing the required instructions to the central processing unit are independent operations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |