Forming a semi-recessed metal for better EM and Planarization using a silo mask

Claim 1

A method of forming a conducting layer with improved step coverage and planarization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching a trench into said insulating layer where said conducting layer is to be deposited using a silo mask as a pattern; etching through said insulating layer within said trench to said underlying semiconductor device structures to form a contact opening using a conducting layer mask as a pattern wherein said silo mask is a reversed tone copy of said conducting layer mask; and depositing said conducting layer overlying said insulating layer within said trench and within said contact opening wherein said conducting layer is partially buried within said insulating layer within said trench whereby planarization is improved because of the reduced step height of said conducting layer.

Claim 2

A method of forming a conducting layer with improved step coverage and planarization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; etching a trench into said insulating layer where said conducting layer is to be deposited using a silo mask as a pattern; etching through said insulating layer within said trench to said underlying semiconductor device structures to form a contact opening using a conducting layer mask as a pattern wherein said silo mask is a reversed tone copy of said conducting layer mask; and depositing said conducting layer overlying said insulating layer within said trench and within said contact opening wherein said conducting layer is partially buried within said insulating layer within said trench whereby planarization is improved because of the reduced step height of said conducting layer.

Claim 14

A method of forming a conducting layer with improved step coverage and planarization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; covering said insulating layer with a first photoresist layer and patterning said first photoresist layer using a silo mask wherein said silo mask is a reverse tone copy of a conducting layer mask to be used for patterning said conducting layer wherein said first photoresist layer is removed where said conducting layer is to be formed; etching a trench into said insulating layer not covered by said first photoresist layer; removing said first photoresist layer; covering said insulating layer with a second photoresist layer and patterning said second photoresist layer with said conducting layer mask wherein said second photoresist layer is removed leaving an opening where said conducting layer is to be deposited and wherein said opening is within said trench and is narrower than said trench; etching through said insulating layer not covered by said second photoresist layer to said underlying semiconductor device structures to form a contact opening; removing said second photoresist layer; and depositing said conducting layer overlying said insulating layer within said trench and within said contact opening wherein said conducting layer is partially buried within said insulating layer within said trench whereby planarization is improved because of the reduced step height of said conducting layer.

Claim 15

A method of forming a conducting layer with improved step coverage and planarization in the fabrication of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing an insulating layer overlying said semiconductor device structures; covering said insulating layer with a first photoresist layer and patterning said first photoresist layer using a silo mask wherein said silo mask is a reverse tone copy of a conducting layer mask to be used for patterning said conducting layer wherein said first photoresist layer is removed where said conducting layer is to be formed; etching a trench into said insulating layer not covered by said first photoresist layer; removing said first photoresist layer; covering said insulating layer with a second photoresist layer and patterning said second photoresist layer with said conducting layer mask wherein said second photoresist layer is removed leaving an opening where said conducting layer is to be deposited and wherein said opening is within said trench and is narrower than said trench; etching through said insulating layer not covered by said second photoresist layer to said underlying semiconductor device structures to form a contact opening; removing said second photoresist layer; and depositing said conducting layer overlying said insulating layer within said trench and within said contact opening wherein said conducting layer is partially buried within said insulating layer within said trench whereby planarization is improved because of the reduced step height of said conducting layer.