Method for fabricating true LDD devices in a MOS technology

Claim 1

A method of fabricating a true-LDD MOS transistor in a transistor structure which includes a transistor region of a semiconductor substrate, a gate structure overlying the transistor region, a source region of the transistor region flanking the gate structure on a first side, and a drain region of the transistor region flanking the gate structure to a second side opposite to the first side, the method comprising the steps of: forming an LDD photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure and extending to cover the source region; implanting a lightly doped ion implant in the drain region which is self-aligned with the gate structure; removing the LDD photoresist mask; forming a spacer on the source side and a spacer on the drain side of the gate structure; implanting a heavily doped ion implant in the source region and the drain region which are self-aligned with the gate structure and spacers; forming a source-only photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure and extending to cover the drain region; implanting a heavily doped ion implant in the source region which is self-aligned with the gate structure; and removing the source-only photoresist mask.

Claim 2

A method of fabricating a true-LDD MOS transistor in a transistor structure which includes a transistor region of a semiconductor substrate, a gate structure overlying the transistor region, a source region of the transistor region flanking the gate structure on a first side, and a drain region of the transistor region flanking the gate structure to a second side opposite to the first side, the method comprising the steps of: forming an LDD photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure and extending to cover the source region; implanting a lightly doped ion implant in the drain region which is self-aligned with the gate structure; removing the LDD photoresist mask; forming a spacer on the source side and a spacer on the drain side of the gate structure; implanting a heavily doped ion implant in the source region and the drain region which are self-aligned with the gate structure and spacers; forming a source-only photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure and extending to cover the drain region; implanting a heavily doped ion implant in the source region which is self-aligned with the gate structure; and removing the source-only photoresist mask.

Claim 8

A method of fabricating a plurality of true-LDD CMOS transistors including a transistor of a first conductivity type and a transistor of a second conductivity type opposite to the first conductivity type, each transistor being formed in a transistor structure which includes a transistor region of a semiconductor substrate, a gate structure overlying the transistor region, a source region of the transistor region flanking the gate structure on a first side, and a drain region of the transistor region flanking the gate structure to a second side opposite to the first side, the method comprising the steps of: forming a first-conductivity-type LDD photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure of the first conductivity type transistor and extending to cover the source region of the first conductivity type transistor and extending to cover the entire transistor region of the second conductivity type transistor; implanting a lightly doped ion implant in the first conductivity type transistor drain region which is self-aligned with the gate structure; removing the first-conductivity-type LDD photoresist mask; forming a second-conductivity-type LDD photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure of the second conductivity type transistor and extending to cover the source region of the second conductivity type transistor and extending to cover the entire transistor region of the first conductivity type transistor; implanting a lightly doped ion implant in the second conductivity type transistor drain region which is self-aligned with the gate structure; removing the second-conductivity-type LDD photoresist mask; forming spacers on the source sides and spacers on the drain sides of the gate structures; forming a first-conductivity-type source/drain photoresist mask layer on the semiconductor substrate, the mask extending to cover the entire transistor region of the second conductivity type transistor; implanting a first-conductivity-type heavily doped ion implant in the first-conductivity-type source and drain regions which are self-aligned with the gate structure and spacers; forming a second-conductivity-type source/drain photoresist mask layer on the semiconductor substrate, the mask extending to cover the entire transistor region of the first conductivity type transistor; and implanting a second-conductivity-type heavily doped ion implant in the second-conductivity-type source and drain regions which are self-aligned with the gate structure and spacers.

Claim 9

A method of fabricating a plurality of true-LDD CMOS transistors including a transistor of a first conductivity type and a transistor of a second conductivity type opposite to the first conductivity type, each transistor being formed in a transistor structure which includes a transistor region of a semiconductor substrate, a gate structure overlying the transistor region, a source region of the transistor region flanking the gate structure on a first side, and a drain region of the transistor region flanking the gate structure to a second side opposite to the first side, the method comprising the steps of: forming a first-conductivity-type LDD photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure of the first conductivity type transistor and extending to cover the source region of the first conductivity type transistor and extending to cover the entire transistor region of the second conductivity type transistor; implanting a lightly doped ion implant in the first conductivity type transistor drain region which is self-aligned with the gate structure; removing the first-conductivity-type LDD photoresist mask; forming a second-conductivity-type LDD photoresist mask layer on the semiconductor substrate, the mask having a boundary aligned to the gate structure of the second conductivity type transistor and extending to cover the source region of the second conductivity type transistor and extending to cover the entire transistor region of the first conductivity type transistor; implanting a lightly doped ion implant in the second conductivity type transistor drain region which is self-aligned with the gate structure; removing the second-conductivity-type LDD photoresist mask; forming spacers on the source sides and spacers on the drain sides of the gate structures; forming a first-conductivity-type source/drain photoresist mask layer on the semiconductor substrate, the mask extending to cover the entire transistor region of the second conductivity type transistor; implanting a first-conductivity-type heavily doped ion implant in the first-conductivity-type source and drain regions which are self-aligned with the gate structure and spacers; forming a second-conductivity-type source/drain photoresist mask layer on the semiconductor substrate, the mask extending to cover the entire transistor region of the first conductivity type transistor; and implanting a second-conductivity-type heavily doped ion implant in the second-conductivity-type source and drain regions which are self-aligned with the gate structure and spacers.