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US5579352A
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Simplified window de-skewing in a serial data receiver
Assignee: National Semiconductor Corp
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Filing: 1994-04-06
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Granted: 1996-11-26
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Expires: 2014-04-06
Abstract
Abstract A serial data receiver includes a clock recovery circuit, a data latch, and a selectable clock inversion mechanism coupled between the clock recovery circuit and the data latch. In one embodiment, the selectable clock inversion mechanism includes an XNOR gate. If a high signal is provided to the XNOR gate, the XNOR gate provides the signal on a recovered clock line to the data latch, thereby placing the window boundaries coincident with, or very near, the rising edges of the input data pulses. The variable phase between these signals is then adjusted for the maximum coincidence of data pulses with the window boundaries. Then, a low signal is provided to the XNOR gate, thereby providing the true signal on the recovered clock line to the data latch. Assuming the symmetry of the recovered clock is truly 50/50, the window moves by exactly 180 degrees. In this manner, the data bits' mean position falls precisely in center of the window, thereby providing substantially ideal window symmetry with minimal phase adjustment and significantly reduced calibration time.
Inventors
- 👤 William D. Llewellyn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:08
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
131 words
A serial data receiver for extracting synchronized data from a binary input signal, said receiver comprising: a clock recovery circuit extracting a recovered clock signal from said binary input signal; a data latch providing a synchronized data signal; and a switching mechanism selectively providing said recovered clock signal to said data latch in a de-skew mode or an inverted recovered clock signal to said data latch in a normal operation mode, said mechanism comprising a recovered clock input for receiving said recovered clock signal from said clock recovery circuit, a select input receiving a select signal, and an output coupled to said data latch; wherein said select signal on said select input determines which of said recovered clock signal or said inverted recovered clock signal is provided to said data latch.
Claim 2
Dependent Claim
131 words
A serial data receiver for extracting synchronized data from a binary input signal, said receiver comprising: a clock recovery circuit extracting a recovered clock signal from said binary input signal; a data latch providing a synchronized data signal; and a switching mechanism selectively providing said recovered clock signal to said data latch in a de-skew mode or an inverted recovered clock signal to said data latch in a normal operation mode, said mechanism comprising a recovered clock input for receiving said recovered clock signal from said clock recovery circuit, a select input receiving a select signal, and an output coupled to said data latch; wherein said select signal on said select input determines which of said recovered clock signal or said inverted recovered clock signal is provided to said data latch.
Claim 3
Dependent Claim
17 words
The serial data receiver of claim 1 wherein said clock recovery circuit includes a phase-locked loop (PLL).
Claim 4
Dependent Claim
18 words
The serial data receiver of claim 2 wherein said phase locked loop includes means for deskewing a window.
Claim 5
Dependent Claim
19 words
The serial data receiver of claim 3 wherein said means for deskewing a window includes a charge-pump-based phase detector.
Claim 6
Dependent Claim
14 words
The serial data receiver of claim 1 wherein said mechanism includes a logic gate.
Claim 7
Dependent Claim
16 words
The serial data receiver of claim 5 wherein said logic gate is an exclusive NOR gate.
Claim 8
Dependent Claim
16 words
The serial data receiver of claim 5 wherein said logic gate is an exclusive OR gate.
Claim 9
Dependent Claim
22 words
The serial data receiver of claim 1 wherein said mechanism includes a two input multiplexer, wherein one input terminal inverts a signal.
Claim 10
Dependent Claim
17 words
The serial data receiver of claim 1 wherein said serial data receiver provides clock symmetry-based window centering.
Claim 11
Dependent Claim
17 words
The serial data receiver of claim 1 wherein said serial data receiver provides delay line-based window centering.
Claim 12
Dependent Claim
130 words
A serial data receiver for providing synchronized data from a binary input signal, said receiver comprising: a clock recovery circuit extracting a recovered clock signal from said binary input signal; a data latch providing a synchronized data signal; and means for selectively providing said recovered clock signal to said data latch in a de-skew mode or an inverted recovered clock signal to said data latch in a normal operation mode, said means comprising a recovered clock input for receiving said recovered clock signal from said clock recovery circuit, a select input receiving a select signal, and an output coupled to said data latch; wherein said select signal on said select input determines whether said means provides said recovered clock signal or said inverted recovered clock signal to said data latch.
Claim 13
Dependent Claim
130 words
A serial data receiver for providing synchronized data from a binary input signal, said receiver comprising: a clock recovery circuit extracting a recovered clock signal from said binary input signal; a data latch providing a synchronized data signal; and means for selectively providing said recovered clock signal to said data latch in a de-skew mode or an inverted recovered clock signal to said data latch in a normal operation mode, said means comprising a recovered clock input for receiving said recovered clock signal from said clock recovery circuit, a select input receiving a select signal, and an output coupled to said data latch; wherein said select signal on said select input determines whether said means provides said recovered clock signal or said inverted recovered clock signal to said data latch.
Claim 14
Dependent Claim
42 words
The serial data receiver of claim 11 wherein said data latch includes a plurality of flip-flops, wherein a first flip-flop receives a delayed data signal, and a second flip-flop and a third flip-flop receive a signal from said means for alternatively inverting.
Claim 15
Dependent Claim
17 words
The serial data receiver of claim 11 wherein said serial data receiver provides clock symmetry-based window centering.
Claim 16
Dependent Claim
17 words
The serial data receiver of claim 11 wherein said serial data receiver provides delay line-based window centering.
Claim 17
Dependent Claim
28 words
The serial data receiver of claim 11, wherein said clock recovery circuit comprises a phase locked loop, and wherein said phase locked loop includes a charge-pump-based phase detector.
Claim 18
Dependent Claim
123 words
A serial data receiver for providing synchronized data from a binary input signal, said receiver comprising: a clock recovery circuit extracting a recovered clock signal from said binary input signal; a data latch providing a synchronized data signal; and means for selectively inverting said recovered clock signal coupled between said clock recovery circuit and said data latch, wherein said means for selectively inverting comprises an inverting input providing an inverted recovered clock signal during a normal operation mode, a non-inverting input providing a non-inverted recovered clock signal during a de-skew mode, a select input, and an output node, wherein a signal on said select input determines which of said inverted clock signal and said non-inverted clock signal is presented on said output node.
Claim 19
Dependent Claim
123 words
A serial data receiver for providing synchronized data from a binary input signal, said receiver comprising: a clock recovery circuit extracting a recovered clock signal from said binary input signal; a data latch providing a synchronized data signal; and means for selectively inverting said recovered clock signal coupled between said clock recovery circuit and said data latch, wherein said means for selectively inverting comprises an inverting input providing an inverted recovered clock signal during a normal operation mode, a non-inverting input providing a non-inverted recovered clock signal during a de-skew mode, a select input, and an output node, wherein a signal on said select input determines which of said inverted clock signal and said non-inverted clock signal is presented on said output node.
Claim 20
Dependent Claim
17 words
The serial data receiver of claim 16 wherein said means for selectively inverting includes a two-input multiplexer.
Claim 21
Independent Claim
79 words
A method of window de-skewing in a serial data receiver, said receiver for providing synchronized data from a binary input signal, said method comprising the steps of: recovering a clock signal from said binary input signal; inverting said recovered clock signal; providing said inverted recovered clock signal to a data latch; maximizing coincidence of a plurality of input signal pulses and data window boundaries; reinverting said recovered clock signal; and providing said recovered clock signal to said data latch.
Claim 22
Independent Claim
79 words
A method of window de-skewing in a serial data receiver, said receiver for providing synchronized data from a binary input signal, said method comprising the steps of: recovering a clock signal from said binary input signal; inverting said recovered clock signal; providing said inverted recovered clock signal to a data latch; maximizing coincidence of a plurality of input signal pulses and data window boundaries; reinverting said recovered clock signal; and providing said recovered clock signal to said data latch.
Claim 23
Dependent Claim
22 words
The method of claim 18, wherein the step of maximizing coincidence includes observing a bit error rate of the input signal pulses.
Claim 24
Dependent Claim
23 words
The method of claim 18, wherein the step of maximizing coincidence further includes adjusting the coincidence to achieve a particular bit error rate.
Claim 25
Dependent Claim
14 words
The method of claim 20, wherein the particular bit error rate is approximately 50%.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |