CMOS circuit for improved power-on reset timing

Claim 1

A power-on reset circuit for a semiconductor integrated circuit, comprising: discharging means for fully discharging a first intermediate signal when a first power supply voltage is low and generating a first constant voltage of a power-on reset signal when the first power supply voltage is high; delaying means for receiving the first intermediate signal, maintaining the power-on reset signal at the constant voltage for a predetermined time after the first power supply voltage is raised above a first predetermined voltage, and generating a second intermediate signal; first inverting means for receiving and inverting the second intermediate signal; and buffering means for receiving the output of the first inverting means and outputting the power-on reset signal at a second constant voltage after the first power supply voltage is raised above a second predetermined voltage, wherein said discharging means comprises first, second, third and fourth transistors each having a gate, first drain/source and second drain/source, wherein said power supply voltage is connected to the first drain/source of said first transistor and the gate and first drain/source of said third transistor, wherein the gate and second drain/source of said first transistor, the second drain/source of said third transistor, the first drain/source of said second transistor and the first drain/source of said fourth transistor are commonly connected, and wherein the gate of said second transistor is connected to a first applied voltage, the second drain/source of said second transistor and the gate and second drain/source of said fourth transistor are connected to ground potential.