Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
215 words
A circuit for detecting when an input voltage exceeds a predetermined threshold, comprising: an input for receiving the input voltage; and a plurality of switching devices, wherein each of said switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path, said plurality comprising: a first switching device having said first terminal coupled to said input and said second terminal coupled to a first node; a second switching device having said first terminal coupled to said first node and said second terminal coupled to a second node; and a third switching device having said first terminal coupled to said second node, wherein each of said first, second and third switching devices are of like conductively type, and wherein said second node provides a first voltage if the input voltage is below the redetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold; wherein: said third terminal of said first switching device is coupled to said first node; said third terminal of said second switching device is coupled for receiving a high voltage source; and said second and third terminals of said third switching device are coupled for receiving a low voltage source.
Claim 2
Dependent Claim
215 words
A circuit for detecting when an input voltage exceeds a predetermined threshold, comprising: an input for receiving the input voltage; and a plurality of switching devices, wherein each of said switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path, said plurality comprising: a first switching device having said first terminal coupled to said input and said second terminal coupled to a first node; a second switching device having said first terminal coupled to said first node and said second terminal coupled to a second node; and a third switching device having said first terminal coupled to said second node, wherein each of said first, second and third switching devices are of like conductively type, and wherein said second node provides a first voltage if the input voltage is below the redetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold; wherein: said third terminal of said first switching device is coupled to said first node; said third terminal of said second switching device is coupled for receiving a high voltage source; and said second and third terminals of said third switching device are coupled for receiving a low voltage source.
Claim 3
Dependent Claim
54 words
The circuit for detecting of claim 1, and further comprising: an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; and a switching circuit coupled between said second node and said output and for providing said representative signal in response to a voltage at said second node.
Claim 4
Dependent Claim
22 words
The circuit for detecting of claim 1 wherein said first, second and third switching devices comprise P type semiconductor field effect transistors.
Claim 5
Dependent Claim
90 words
The circuit for detecting of claim 1, and further comprising: an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; a fourth switching device having said first terminal coupled for receiving a high voltage source, said second terminal coupled to said output, and said third terminal coupled to said second node; and a fifth switching device having said first terminal coupled for receiving a low voltage source, said second terminal coupled to said output, and said third terminal coupled to said second node.
Claim 6
Dependent Claim
32 words
The circuit for detecting of claim 4 wherein said fourth switching device comprises a P channel field effect transistor and wherein said fifth switching device comprises an N channel field effect transistor.
Claim 7
Dependent Claim
110 words
The circuit for detecting of claim 1, and further comprising: an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; a fourth switching device having said first terminal coupled for receiving a high voltage source, said second terminal coupled to said output, and said third terminal coupled to said second node; a fifth switching device having said first terminal coupled to said output, and said third terminal coupled to said second node; and a sixth switching device having said first terminal coupled to said second terminal of said fifth switching device, and said second and third terminals for receiving a low voltage source.
Claim 8
Dependent Claim
34 words
The circuit for detecting of claim 6 wherein said fourth and said sixth switching devices comprise P channel field effect transistors, and wherein said firth switching device comprises an N channel field effect transistor.
Claim 9
Dependent Claim
163 words
The circuit for detecting of claim 1, and further comprising: an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; a fourth switching device having said first terminal coupled for receiving a high voltage source, said second terminal coupled to said output, and said third terminal coupled to said second node; a fifth switching device having said first terminal coupled to said output, and said third terminal coupled to said second node; a sixth switching device having said first terminal coupled to said second terminal of said fifth switching device, and said second and third terminals for receiving a low voltage source; a seventh switching device having said first terminal coupled to said second terminal of said fifth switching device, and said second terminal for receiving a low voltage source; and an inverting circuit having an inverter input coupled to said output and an inverter output coupled to said third terminal of said seventh switching device.
Claim 10
Dependent Claim
34 words
The circuit for detecting of claim 8 wherein said fifth and seventh switching devices comprise N channel field effect transistors, and wherein said fourth and sixth switching devices comprise P channel field effect transistors.
Claim 11
Dependent Claim
83 words
The circuit for detecting of claim 8 wherein said inverting circuit comprises: an eighth switching device having said first terminal coupled for receiving a high voltage, said second terminal coupled to said third terminal of said seventh switching device and said third terminal coupled to said output; and a ninth switching device having said first terminal coupled to said second terminal of said seventh switching device, said second terminal coupled for receiving a low voltage and said third terminal coupled to said output.
Claim 12
Dependent Claim
32 words
The circuit for detecting of claim 10 wherein said eighth switching device comprises a P channel field effect transistor and wherein said ninth switching device comprises an N channel field effect transistor.
Claim 13
Dependent Claim
19 words
The circuit for detecting of claim 1 wherein said first, second and third switching devices comprise field effect transistors.
Claim 14
Dependent Claim
158 words
A circuit for detecting when an input voltage exceeds a predetermined threshold, comprising: an input for receiving the input voltage; and a first P channel transistor having a source coupled to said input and a drain coupled to a first node; a second P channel transistor having a source coupled to said first node and a drain coupled to a second node; and a third P channel transistor having a source coupled to said second node, and wherein said second node provides a first voltage if the input voltage is below the predetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold; wherein: a gate of said first P channel transistor is coupled to said first node; a gate of said second P channel transistor is coupled for receiving a high voltage source; and a drain and gate of said third P channel transistor are coupled for receiving a low voltage source.
Claim 15
Dependent Claim
158 words
A circuit for detecting when an input voltage exceeds a predetermined threshold, comprising: an input for receiving the input voltage; and a first P channel transistor having a source coupled to said input and a drain coupled to a first node; a second P channel transistor having a source coupled to said first node and a drain coupled to a second node; and a third P channel transistor having a source coupled to said second node, and wherein said second node provides a first voltage if the input voltage is below the predetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold; wherein: a gate of said first P channel transistor is coupled to said first node; a gate of said second P channel transistor is coupled for receiving a high voltage source; and a drain and gate of said third P channel transistor are coupled for receiving a low voltage source.
Claim 16
Dependent Claim
158 words
The circuit for detecting of claim 13, and further comprising: an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; a fourth P channel transistor having a source coupled for receiving a high voltage source, a drain coupled to said output, and a gate coupled to said second node; a first N channel transistor having a source coupled to said output, and a gate coupled to said second node; a fifth P channel transistor having a source coupled to a drain of said first N channel transistor, and a drain and gate for receiving a low voltage source; a second N channel transistor having a drain coupled to said drain of said first N channel transistor, and a source for receiving a low voltage source; and an inverting circuit having an inverter input coupled to said output and an inverter output coupled to said gate of said second N channel transistor.
Claim 17
Dependent Claim
53 words
The circuit for detecting claim 14, and further comprising: an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; and a switching circuit coupled between said second node and said output and for providing said representative signal in response to a voltage at said second node.
Claim 18
Dependent Claim
256 words
A circuit for detecting when an input voltage exceeds a predetermined threshold, comprising: an input for receiving the input voltage; and a first P channel transistor having a source coupled to said input and a drain coupled to a first node; a second P channel transistor having a source coupled to said first node and a drain coupled to a second node; a third P channel transistor having a source coupled to said second node, and wherein said second node provides a first voltage if the input voltage is below the predetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold; an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; a fourth P channel transistor having a source coupled for receiving a high voltage source, a drain coupled to said output, and a gate coupled to said second node; a first N channel transistor having a source coupled to said output, and a gate coupled to said second node; a fifth P channel transistor having a source coupled to said a drain of said first N channel transistor, and a drain and gate for receiving a low voltage source; a second N channel transistor having a drain coupled to said drain of said first N channel transistor, and a source for receiving a low voltage source; and an inverting circuit having an inverter input coupled to said output and an inverter output coupled to said gate of said second N channel transistor.
Claim 19
Dependent Claim
256 words
A circuit for detecting when an input voltage exceeds a predetermined threshold, comprising: an input for receiving the input voltage; and a first P channel transistor having a source coupled to said input and a drain coupled to a first node; a second P channel transistor having a source coupled to said first node and a drain coupled to a second node; a third P channel transistor having a source coupled to said second node, and wherein said second node provides a first voltage if the input voltage is below the predetermined threshold and provides a second voltage if the input voltage is above the predetermined threshold; an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; a fourth P channel transistor having a source coupled for receiving a high voltage source, a drain coupled to said output, and a gate coupled to said second node; a first N channel transistor having a source coupled to said output, and a gate coupled to said second node; a fifth P channel transistor having a source coupled to said a drain of said first N channel transistor, and a drain and gate for receiving a low voltage source; a second N channel transistor having a drain coupled to said drain of said first N channel transistor, and a source for receiving a low voltage source; and an inverting circuit having an inverter input coupled to said output and an inverter output coupled to said gate of said second N channel transistor.
Claim 20
Dependent Claim
54 words
The circuit for detecting of claim 16, and further comprising: an output for providing a representative signal indicative of whether the input voltage exceeds the predetermined voltage; and a switching circuit coupled between said second node and said output and for providing said representative signal in response to a voltage at said second node.
Claim 21
Dependent Claim
57 words
The circuit for detecting of claim 16 wherein: a gate of said first P channel transistor is coupled to said first node; a gate of said second P channel transistor is coupled for receiving a high voltage source; and a drain and gate of said third P channel transistor are coupled for receiving a low voltage source.