Vertical power MOSFET and process of fabricating the same

Claim 1

A process of fabricating a vertical MOSFET comprising the steps of: forming a first semiconductor layer of a first conductivity type on a major surface of a semiconductor substrate of the first conductivity type, said first semiconductor layer functioning as a drain region; selectively introducing impurities of a second conductivity type into a surface region of the first semiconductor layer, thereby forming a second semiconductor layer of the second conductivity type functioning as a channel region; selectively introducing impurities of the first conductivity type into a surface region of the second semiconductor layer, thereby forming a third semiconductor layer of the first conductivity type functioning as a source region; forming at least one trench extending from the surface of the third semiconductor layer and penetrating the second semiconductor layer such that a bottom portion of said trench reaches the first semiconductor layer; forming a first insulating film on at least the bottom portion of the trench; depositing an ion implantation mask layer on said first insulating film such that said trench is filled, and etching back said ion implantation mask layer so that said ion implantation mask layer remains up to an intermediate portion of said trench; removing that portion of the first insulating film, which is exposed to the trench; implanting channel ions into an exposed inner wall of the trench in a slanting direction; forming a second insulating film on said ion implantation mask layer and on the exposed inner wall of said trench, said second insulating film functioning as a gate insulating film; depositing a conductor layer entirely on the second insulating film such that said trench is filled; and removing said conductor layer such that said conductor layer is left at least in said trench, thereby forming a gate lead-out electrode.