Method for decreasing penalty resulting from a cache miss in multi-level cache system

Claim 2

In a computing system which includes a processor, a main memory, a first level cache and a second level cache, the second level cache containing data lines, and each valid entry within the first level cache containing a data line fragment of a data line within the second level cache, each data line fragment contained within the first level cache including a fragment, but not all, of a data line contained within the second level cache, a method which is performed when a first level cache miss and a second level cache miss results from a cache reference of a data word made by the processor, the method comprising the steps of: (a) fetching a new data line from the main memory; (b) while waiting for the new data line fetched in step (a) to arrive from the main memory, determining which entries of rile first level cache are invalid; and, (c) when the new data line arrives from the main memory, placing into the first level cache a data line fragment which includes the data word, end in addition placing into the first level cache at least one additional data line fragment which replaces an entry determined in step (b) to be invalid; wherein concurrent with step (c) the new data line is placed in the second level cache, replacing a second level victim cache line within the second level cache.

Claim 3

A method as in claim 1 wherein in step (b) invalid entries include entries of the first level cache which are marked invalid and entries within the first level cache which contain cache line fragments from the second level victim cache line within the second level cache.

Claim 4

A method as in claim 1 wherein each second level cache line contains sixteen words and each first level cache line fragment contains four words.

Claim 5

A method as in claim 1 wherein in step (b) invalid entries include entries of the first level cache which are marked invalid and entries within the first level cache which contain cache line fragments from a second level victim cache line within the second level cache.

Claim 6

A computing system comprising; a processor; a main memory; a first level cache; a second level cache, the second level cache containing data lines and valid entries within the first level cache each containing a data line fragment of a dam line within the second level cache, each data line fragment contained within the first level cache including a fragment, but not all, of a data line contained within the second level cache; and, a cache controller, coupled to the processor, the main memory, the first level cache and the second level cache, the cache controller fetching a new dam line from the main memory when a first level cache miss and a second level cache miss results from a cache reference of a data word made by the processor, determining which entries of the first level cache are invalid, and placing into the first level cache a data line fragment which includes the data word and in addition replacing as many data line fragments as possible from the new data line into invalid entries in the first level cache when the new data line arrives from the main memory; wherein the cache controller additionally replaces a second level victim cache line within the second level cache concurrent with the cache controller placing as many data line fragments as possible from the new data line into invalid entries in the first level cache.

Claim 7

A computing system comprising; a processor; a main memory; a first level cache; a second level cache, the second level cache containing data lines and valid entries within the first level cache each containing a data line fragment of a dam line within the second level cache, each data line fragment contained within the first level cache including a fragment, but not all, of a data line contained within the second level cache; and, a cache controller, coupled to the processor, the main memory, the first level cache and the second level cache, the cache controller fetching a new dam line from the main memory when a first level cache miss and a second level cache miss results from a cache reference of a data word made by the processor, determining which entries of the first level cache are invalid, and placing into the first level cache a data line fragment which includes the data word and in addition replacing as many data line fragments as possible from the new data line into invalid entries in the first level cache when the new data line arrives from the main memory; wherein the cache controller additionally replaces a second level victim cache line within the second level cache concurrent with the cache controller placing as many data line fragments as possible from the new data line into invalid entries in the first level cache.

Claim 8

A computing system as in claim 5 wherein invalid entries as determined by the cache controller include entries of the first level cache which are marked invalid and entries within the first level cache which contain cache line fragments from the second level victim cache line within the second level cache.

Claim 9

A computing system as in claim 5 wherein each second level cache line contains sixteen words and each first level cache line fragment contains four words.

Claim 10

A computing system as in claim 5 wherein invalid entries as determined by the cache controller include entries of the first level cache which are marked invalid and entries within the first level cache which contain cache line fragments from a second level victim cache line within the second level cache.

Claim 11

In a computing system which includes a processor, a main memory, a first level cache and a second level cache, the second level cache containing data lines and the first level cache containing within valid entries data line fragments of data lines within the second level cache, each data line fragment contained within the first level cache including a fragment, but not all, of a data line contained within the second level cache, a method comprising the steps of: (a) in response to a processor attempt to access a data word, searching for the data word in the first level cache; (b) when a first level cache miss results from performance of step (a), searching for the data word in the second level cache; and, (c) when a second level cache miss results from the performance of step (b), performing the following substeps: (c.1) fetching a new data line from the main memory, the new data line containing the data word, (c.2) while waiting for the new data line fetched in substep (c.1) to arrive from the main memory, determining which entries of the first level cache are invalid, and (c.3) when the new data line is fetched from the main memory, placing as many data line fragments as possible from the new data line into invalid entries in the first level cache, one data line fragment from the new data line placed into the first level cache including the data word; wherein concurrent with substep (c.3) the new data line is placed in the second level cache, replacing a second level victim cache line within the second level cache.

Claim 12

In a computing system which includes a processor, a main memory, a first level cache and a second level cache, the second level cache containing data lines and the first level cache containing within valid entries data line fragments of data lines within the second level cache, each data line fragment contained within the first level cache including a fragment, but not all, of a data line contained within the second level cache, a method comprising the steps of: (a) in response to a processor attempt to access a data word, searching for the data word in the first level cache; (b) when a first level cache miss results from performance of step (a), searching for the data word in the second level cache; and, (c) when a second level cache miss results from the performance of step (b), performing the following substeps: (c.1) fetching a new data line from the main memory, the new data line containing the data word, (c.2) while waiting for the new data line fetched in substep (c.1) to arrive from the main memory, determining which entries of the first level cache are invalid, and (c.3) when the new data line is fetched from the main memory, placing as many data line fragments as possible from the new data line into invalid entries in the first level cache, one data line fragment from the new data line placed into the first level cache including the data word; wherein concurrent with substep (c.3) the new data line is placed in the second level cache, replacing a second level victim cache line within the second level cache.

Claim 13

A method as in claim 9 wherein in substep (c.2) invalid entries include entries of the first level cache which are marked invalid and entries within the first level cache which contain cache line fragments from the second level victim cache line within the second level cache.

Claim 14

A method as in claim 9 wherein each second level cache line contains sixteen words and each first level cache line fragment contains four words.

Claim 15

A method as in claim 9 wherein in substep (c.2) invalid entries include entries of the first level cache which are marked invalid and entries within the first level cache which contain cache line fragments from a second level victim cache line within the second level cache.