Integrated content addressable read only memory

Claim 1

In a data processing system an integrated content or random addressable read only memory device in which a plurality of binary input data patterns, received by an input station, are converted into binary output address codes, on an output station, where each unique binary input data pattern results in a binary output address code, comprising: means including at least two driver circuits for accepting the binary input data pattern from the input station and generating a true output signal and a false output signal for each binary bit, respectively, in the binary input data pattern through each driver circuit each generating an inverting or false and a non inverting or true output signal; means defining a multiple line selection grid using rows and columns; means for applying the true and the false output signals from each of the driver circuits to the columns of said multiple line selection grid; means defining an array of logical and gates by serial rows of field effect transistors, each field effect transistor representing an input to the logical and gate; means defining connection cells programmable for either connection or non connection; means for connecting either the true or the false output signal from each driver output on the grid to said array of logical and gates via said connection cells so that each logical and gate is connected to a unique binary input data pattern; means defining a diode function; means for generating said binary output address code, when the unique binary input data pattern is applied, from the output of each logical and gate in the array via said diode function and said connection cells; means for directing the resulting binary output address code to an output station.