US5301143A
Expired / Lapsed
US
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Method for identifying a semiconductor die using an IC with programmable links
Assignee: Round Rock Research LLC
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Filing: 1992-12-31
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Granted: 1994-04-05
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Expires: 2012-12-31
Abstract
Abstract A method for identifying a semiconductor die includes a programmable integrated circuit formed on the semiconductor die. The programmable circuit includes FET transistors connected to output nodes and to programmable links such as fuses, anti-fuses or laser programmable links which are connected to ground. A gate element of each transistor is connected to an address line which controls current flow through the transistors to the output nodes. During manufacture, the programmable links can be selectively activated to create an identification code which can be read at the output nodes of the integrated circuit upon input of a predetermined address code.
Inventors
- 👤 Kul Ohri
- 👤 Kevin Duesman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:21
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/20; H; H10; H10W; H10W46/00; H10W46/401; H10W46/403
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
93 words
A method for identifying a semiconductor die comprising; forming a programmable integrated circuit on the die including programmable links connected to output nodes and to an FET transistor; selectively activating the programmable links; addressing the FET transistor with a predetermined address code to control current flow to each output node such that for a given address code and based on a condition of the programmable links a predetermined identification code can be read at the output nodes; and then reading the predetermined identification code at the output nodes to identify the semiconductor die.
Claim 2
Independent Claim
93 words
A method for identifying a semiconductor die comprising; forming a programmable integrated circuit on the die including programmable links connected to output nodes and to an FET transistor; selectively activating the programmable links; addressing the FET transistor with a predetermined address code to control current flow to each output node such that for a given address code and based on a condition of the programmable links a predetermined identification code can be read at the output nodes; and then reading the predetermined identification code at the output nodes to identify the semiconductor die.
Claim 3
Dependent Claim
30 words
The method for identifying a semiconductor die as recited in claim 1 and wherein the programmable links are selected from a group consisting of fuses, anti-fuses or laser programmable links.
Claim 4
Dependent Claim
46 words
The method for identifying a semiconductor die as recited in claim 2 and wherein each programmable link is connected to a pair of FET transistors and a gate element of each transistor is addressable by the address code to control current flow to the output nodes.
Claim 5
Dependent Claim
23 words
The method for identifying a semiconductor die as recited in claim 1 and further comprising precharging the FET transistor using a precharge circuit.
Claim 6
Independent Claim
122 words
A method for identifying a semiconductor die comprising: forming a programmable integrated circuit on the semiconductor die including at least two output nodes with each output node connected to a programmable link and to an FET transistor and with each transistor having a gate element addressable with a predetermined address input to control a current flow to the output nodes; selectively activating the programmable links of the integrated circuit; addressing the gate elements of the transistors with a predetermined address code such that for a given address code and based on a condition of the programmable links a predeterminal identification code can be read at the output nodes; and reading an output signal at the output nodes representative of the identification code.
Claim 7
Independent Claim
122 words
A method for identifying a semiconductor die comprising: forming a programmable integrated circuit on the semiconductor die including at least two output nodes with each output node connected to a programmable link and to an FET transistor and with each transistor having a gate element addressable with a predetermined address input to control a current flow to the output nodes; selectively activating the programmable links of the integrated circuit; addressing the gate elements of the transistors with a predetermined address code such that for a given address code and based on a condition of the programmable links a predeterminal identification code can be read at the output nodes; and reading an output signal at the output nodes representative of the identification code.
Claim 8
Dependent Claim
30 words
The method for identifying a semiconductor die as recited in claim 5 and wherein the programmable links are selected from a group consisting of fuses, anti-fuses or laser programmable links.
Claim 9
Dependent Claim
21 words
The method for identifying a semiconductor die as recited in claim 6 and wherein the programmable links are connected to ground.
Claim 10
Dependent Claim
26 words
The method for identifying a semiconductor die as recited in claim 7 and wherein the programmable integrated circuit is a matrix arrangement of rows and columns.
Claim 11
Dependent Claim
36 words
The method for identifying a semiconductor die as recited in claim 8 and wherein the transistor and programmable links are arranged in column lines and the gate elements of the transistor are addressable through address lines.
Claim 12
Dependent Claim
37 words
The method for identifying a semiconductor die as recited in claim 9 and wherein a pair of transistors are connected in series in each column line so that each output node is controlled by two address inputs.
Claim 13
Dependent Claim
20 words
The method for identifying a semiconductor die as recited in claim 10 and wherein some of the transistors are precharged.
Claim 14
Dependent Claim
21 words
The method for identifying a semiconductor die as claimed in claim 11 and wherein a P-channel of the transistors are precharged.
Claim 15
Dependent Claim
27 words
The method of identifying a semiconductor structure as claimed in claim 12 and wherein the identification code identifies a wafer from which the semiconductor die was obtained.
Claim 16
Dependent Claim
147 words
A programmable integrated circuit for identifying a semiconductor die, said circuit formed on the die and comprising: first and second pairs of FET transistors, each pair of FET transistors connected to an output node of a conductive line having multiple output nodes; an address line connected to a gate element of each transistor for controlling current flow through each pair of FET transistors to the output nodes; and first and second programmable links connected to the first and second pairs of transistors respectively and to ground with the programmable links adapted to be selectively activated to create an identification code readable at the output nodes upon input of a predetermined address code to the address lines such that for a given address code and based on a condition of the programmable links a predetermined identification code can be read at the output nodes to identify the die.
Claim 17
Dependent Claim
147 words
A programmable integrated circuit for identifying a semiconductor die, said circuit formed on the die and comprising: first and second pairs of FET transistors, each pair of FET transistors connected to an output node of a conductive line having multiple output nodes; an address line connected to a gate element of each transistor for controlling current flow through each pair of FET transistors to the output nodes; and first and second programmable links connected to the first and second pairs of transistors respectively and to ground with the programmable links adapted to be selectively activated to create an identification code readable at the output nodes upon input of a predetermined address code to the address lines such that for a given address code and based on a condition of the programmable links a predetermined identification code can be read at the output nodes to identify the die.
Claim 18
Dependent Claim
31 words
The integrated circuit as claimed in claim 14 and wherein the programmable links are selected from a group consisting of fuses, voltage programmable anti-fuses, laser programmable anti-fuses, or laser programmable links.
Claim 19
Dependent Claim
17 words
The integrated circuit as claimed in claim 15 and wherein some of the FET transistors are precharged.
Claim 20
Dependent Claim
28 words
The integrated circuit as claimed in claim 16 and wherein the address lines are arranged in rows and the FET transistors and programmable elements are arranged in columns.
Claim 21
Dependent Claim
21 words
The integrated circuit as claimed in claim 17 and wherein there are eight programmable links to provide sixty-four bits of information.
Claim 22
Dependent Claim
17 words
The integrated circuit as claimed in claim 18 and wherein the semiconductor structure is a semiconductor die.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |