Regulator for pumped voltage generator

Claim 2

A voltage regulator comprising: a plurality of capacitors for pumping a supply voltage through a plurality of stages, each capacitor pumping one of said stages, said plurality of capacitors thereby generating an output voltage; a plurality of diodes connected in series, a first diode of said plurality receiving said supply voltage and a last diode of said plurality providing said output voltage; and a comparator for receiving said output voltage, wherein said comparator controls the pumping of at least one of said plurality of capacitors and at least one of said plurality of capacitors is pumped independently from said comparator.

Claim 3

A voltage regulator as in claim 1 in which said comparator causes said plurality of capacitors to pump said output voltage toward a first higher voltage when said output voltage is below a selected level, and said comparator causes said plurality of capacitors to pump said output voltage toward a second lower voltage when said output voltage is above said selected level.

Claim 4

A voltage regulator as in claim 2 wherein each capacitor has a first plate connected to a node between a corresponding pair of said diodes; and means for applying switching signals to a second plate of each capacitor, wherein said switching signals are inverted for each successive capacitor.

Claim 5

A voltage regulator as in claim 3 wherein said plurality of diodes comprises first, second, third, and fourth diodes, said fourth diode supplying said output voltage, wherein said plurality of capacitors comprises first, second, and third capacitors, said first capacitor having its first plate connected to a node between said first and second diodes, said second capacitor having its first plate connected to a node between said second and third diodes, said third capacitor having its first plate connected to a node between said third and fourth diodes, and wherein said means for applying switching signals comprises a clock signal source connected to said third capacitor, and said clock signal source is connected through said comparator for controlling pumping to said first and second capacitors.

Claim 6

A voltage regulator as in claim 3 wherein said comparator has a first input port, a second input port, and an output port, wherein said first input port receives a reference voltage and said second port receives a signal related to said output voltage.

Claim 7

A voltage regulator as in claim 1 further including: a transistor having a first terminal connected to receive said output voltage and a second terminal coupled to a first input node of said comparator, wherein said comparator has a second input node connected to receive a reference voltage, and an output node coupled to the plate of said at least one capacitor; and means for pumping voltage at said second terminal to a high level while said transistor is turned off and to a low level while said transistor is turned on.

Claim 8

A voltage regulator coupled to a voltage supply and providing an output voltage, said voltage regulator comprising: a plurality of capacitors for pumping said supply voltage through a plurality of stages, each capacitor pumping one of said stages; and a feedback system coupled between an output line providing said output voltage and said plurality of capacitors, wherein said system includes: a comparator having a first input port, a second input port, and an output port, wherein said first input port receives a reference voltage and said second input port receives a modified signal, said modified signal being related to said output voltage; and control means connected to said output port of said comparator for determining the signals provided to said plurality of capacitors, wherein said control means comprises: a NAND gate having a first terminal, a second input terminal, and an output terminal; a first inverter which receives a clock signal and provides a signal to said first input terminal of said NAND gate; and a latch having an input terminal, an enable terminal, and an output terminal, wherein said input terminal of said latch is coupled to said output port of said comparator, and said output terminal of said latch is coupled to said second input terminal of said NAND gate, wherein said enable terminal receives said clock signal.

Claim 9

A voltage regulator coupled to a voltage supply and providing an output voltage, said voltage regulator comprising: a plurality of capacitors for pumping said supply voltage through a plurality of stages, each capacitor pumping one of said stages; and a feedback system coupled between an output line providing said output voltage and said plurality of capacitors, wherein said system includes: a comparator having a first input port, a second input port, and an output port, wherein said first input port receives a reference voltage and said second input port receives a modified signal, said modified signal being related to said output voltage; and control means connected to said output port of said comparator for determining the signals provided to said plurality of capacitors, wherein said control means comprises: a NAND gate having a first terminal, a second input terminal, and an output terminal; a first inverter which receives a clock signal and provides a signal to said first input terminal of said NAND gate; and a latch having an input terminal, an enable terminal, and an output terminal, wherein said input terminal of said latch is coupled to said output port of said comparator, and said output terminal of said latch is coupled to said second input terminal of said NAND gate, wherein said enable terminal receives said clock signal.

Claim 10

A voltage regulator coupled to a voltage supply and providing an output voltage, said voltage regulator comprising: plurality of capacitors for pumping said supply voltage through a plurality of stages, each capacitor pumping one of said stages; and a feedback system coupled between an output line providing said output voltage and said plurality of capacitors, wherein said feedback system includes: a comparator having a first input port, a second input port, and an output port, wherein said first input port receives a reference voltage; control means coupled to said output port of said comparator for determining the signals provided to said plurality of capacitors; and means for generating a modified signal coupled between said output line and said second input port, said means for generating comprising: a P-channel transistor having a first terminal, a second terminal, and a gate, said first terminal connected to said output line, and said gate connected to an anode of said last diode; a pair of capacitors connected in series between said second terminal of said P-channel transistor and a first voltage source; and means for discharging said pair of capacitors if said P-channel transistor is off, and not discharging said pair of capacitors if said P-channel transistor is on.

Claim 11

A voltage regulator coupled to a voltage supply and providing an output voltage, said voltage regulator comprising: plurality of capacitors for pumping said supply voltage through a plurality of stages, each capacitor pumping one of said stages; and a feedback system coupled between an output line providing said output voltage and said plurality of capacitors, wherein said feedback system includes: a comparator having a first input port, a second input port, and an output port, wherein said first input port receives a reference voltage; control means coupled to said output port of said comparator for determining the signals provided to said plurality of capacitors; and means for generating a modified signal coupled between said output line and said second input port, said means for generating comprising: a P-channel transistor having a first terminal, a second terminal, and a gate, said first terminal connected to said output line, and said gate connected to an anode of said last diode; a pair of capacitors connected in series between said second terminal of said P-channel transistor and a first voltage source; and means for discharging said pair of capacitors if said P-channel transistor is off, and not discharging said pair of capacitors if said P-channel transistor is on.

Claim 12

The voltage regulator of claim 7 further including a second inverter coupled between said output terminal of said NAND gate and at least one of said plurality of capacitors.