Voltage step-up circuit for non-volatile semiconductor memory

Claim 2

A voltage step-up circuit for a non-volatile semiconductor memory, comprising: an oscillator for generating a high-speed clock signal; a first series of an odd number of inverters connected to said oscillator for inverting said clock signal; a second series of an even number of inverters connected to said oscillator for inverting said clock signal; a series of transistors in cascade connection, which are alternatively turned on by outputs from a respective inverter of said first and second series of inverters wherein; a pre-stage inverter in a final stage of said first series of inverters and second series of inverters connecting a drain of a p-channel transistor to a drain of an n-channel transistor through a transmission gate having two sides, wherein said two sides of said transmission gate are connected to gates of a second p-channel transistor and a second n-channel transistor of the inverters in the final stage respectively; said pre-stage inverters of said first and second series of inverters connect, at a given node, the gates of said p-channel and n-channel transistors to the gates of both sides of said transmission gate; said second series of inverters including at least one first stage inverter turned on in succession when a clock pulse of said clock signal is input to gates of said p-channel and n-channel transistors; and said clock pulse is output to said given node of said second series of inverters through said at least one first stage inverter.

Claim 3

The voltage step-up circuit of claim 1, wherein said transmission gate is made of a MOS transistor.

Claim 4

The voltage step-up circuit of claim 1, wherein said transmission gate is made such that an On voltage is lower than an Off voltage of said final-stage p-channel transistor.

Claim 5

A voltage step-up circuit for a non-volatile semiconductor memory comprising: a plurality of transistors connected in series and wherein a first one of said plurality of transistors is coupled to said non-volatile semiconductor memory; an oscillator; a first series of inverters having an even number of inverters therein and including: (i) a first and a second MOS transistor of a first conductivity type, wherein a gate of said first MOS transistor and a gate of said second MOS transistor are coupled to said oscillator and wherein a drain of said first MOS transistor is coupled to a source of said second MOS transistor, and wherein a source of said first MOS transistor is coupled to a first reference voltage; (ii) a third MOS transistor of a second conductivity type having a gate coupled to said oscillator, a drain coupled to a second reference voltage and a source coupled to a drain of said second MOS transistor; (iii) a fourth MOS transistor of said second conductivity type having a gate coupled to said oscillator, a source coupled to a source of said second MOS transistor, and a drain coupled to said drain of said second MOS transistor; (iv) a fifth MOS transistor of said second conductivity type having a drain coupled to said second reference voltage, a gate coupled to said drain of said second MOS transistor, and a source coupled to first node; (v) a sixth MOS transistor of said first conductivity type having a drain coupled to said first node, a gate coupled to said source of said second MOS transistor, and a source coupled to said first reference voltage; and (vi) wherein said first node is coupled to a first subset of said plurality of transistors; a second series of inverters having an odd number of inverters therein and including: (i) a seventh and an eighth MOS transistor of a first conductivity type, wherein a gate of said seventh MOS transistor and a gate of said eighth MOS transistor are coupled to a second node and wherein a drain of said seventh MOS transistor is coupled to a source of said eighth MOS transistor, and wherein a source of said seventh MOS transistor is coupled to a first reference voltage; (ii) a ninth MOS transistor of said second conductivity type having a gate coupled to said second node, a drain coupled to said second reference voltage and a source coupled to a drain of said eighth MOS transistor; (iii) a tenth MOS transistor of said second conductivity type having a gate coupled to said second node, a source coupled to a source of said eighth MOS transistor, and a drain coupled to said drain of said eighth MOS transistor; (iv) an eleventh MOS transistor of said first conductivity type having a source coupled to said first reference voltage, a gate coupled to said drain of said seventh MOS transistor, and a drain coupled to a third node; (v) a twelfth MOS transistor of said second conductivity type having a source coupled to said third node, a gate coupled to said drain of said eighth MOS transistor, and a drain coupled to said second reference voltage; (vi) wherein said third node is coupled to a second subset of said plurality of transistors; (vii) a thirteenth MOS transistor having a source coupled to said first reference voltage, a gate coupled to said oscillator and a drain coupled to said second node; and (viii) a fourteenth MOS transistor having a source coupled to said second node, a gate coupled to said oscillator, and a drain coupled to said first reference voltage.

Claim 6

A voltage step-up circuit for a non-volatile semiconductor memory comprising: a plurality of transistors connected in series and wherein a first one of said plurality of transistors is coupled to said non-volatile semiconductor memory; an oscillator; a first series of inverters having an even number of inverters therein and including: (i) a first and a second MOS transistor of a first conductivity type, wherein a gate of said first MOS transistor and a gate of said second MOS transistor are coupled to said oscillator and wherein a drain of said first MOS transistor is coupled to a source of said second MOS transistor, and wherein a source of said first MOS transistor is coupled to a first reference voltage; (ii) a third MOS transistor of a second conductivity type having a gate coupled to said oscillator, a drain coupled to a second reference voltage and a source coupled to a drain of said second MOS transistor; (iii) a fourth MOS transistor of said second conductivity type having a gate coupled to said oscillator, a source coupled to a source of said second MOS transistor, and a drain coupled to said drain of said second MOS transistor; (iv) a fifth MOS transistor of said second conductivity type having a drain coupled to said second reference voltage, a gate coupled to said drain of said second MOS transistor, and a source coupled to first node; (v) a sixth MOS transistor of said first conductivity type having a drain coupled to said first node, a gate coupled to said source of said second MOS transistor, and a source coupled to said first reference voltage; and (vi) wherein said first node is coupled to a first subset of said plurality of transistors; a second series of inverters having an odd number of inverters therein and including: (i) a seventh and an eighth MOS transistor of a first conductivity type, wherein a gate of said seventh MOS transistor and a gate of said eighth MOS transistor are coupled to a second node and wherein a drain of said seventh MOS transistor is coupled to a source of said eighth MOS transistor, and wherein a source of said seventh MOS transistor is coupled to a first reference voltage; (ii) a ninth MOS transistor of said second conductivity type having a gate coupled to said second node, a drain coupled to said second reference voltage and a source coupled to a drain of said eighth MOS transistor; (iii) a tenth MOS transistor of said second conductivity type having a gate coupled to said second node, a source coupled to a source of said eighth MOS transistor, and a drain coupled to said drain of said eighth MOS transistor; (iv) an eleventh MOS transistor of said first conductivity type having a source coupled to said first reference voltage, a gate coupled to said drain of said seventh MOS transistor, and a drain coupled to a third node; (v) a twelfth MOS transistor of said second conductivity type having a source coupled to said third node, a gate coupled to said drain of said eighth MOS transistor, and a drain coupled to said second reference voltage; (vi) wherein said third node is coupled to a second subset of said plurality of transistors; (vii) a thirteenth MOS transistor having a source coupled to said first reference voltage, a gate coupled to said oscillator and a drain coupled to said second node; and (viii) a fourteenth MOS transistor having a source coupled to said second node, a gate coupled to said oscillator, and a drain coupled to said first reference voltage.

Claim 7

The voltage step-up circuit of claim 4 wherein said MOS transistor of said first conductivity type is a P MOS transistor.

Claim 8

The voltage step-up circuit of claim 4 wherein said MOS transistor of said second conductivity type is an N MOS transistor.

Claim 9

The voltage step-up circuit of claim 4 further comprising: a first set of capacitors disposed between said first node and said first subset of said plurality of transistors; and a second set of capacitors disposed between said third node and said second subset of said plurality of transistors.