US4820936A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated CMOS circuit comprising a substrate bias voltage generator
Assignee: US Philips Corp
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Filing: 1987-09-08
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Granted: 1989-04-11
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Expires: 2007-09-08
Abstract
Abstract In CMOS integrated circuits, "latch-up" problems may arise if no special steps are taken. One way to counteract a "latch-up" state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to "latch-up", especially during measuring and testing procedures, in which no external clock signal is supplied.
Inventors
- 👤 Hendrikus J. M. Veendrick
- 👤 Cornelis G. L. M. Van Der Sanden
- 👤 Arie Slob
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:34
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
99 words
An integrated CMOS circuit comprising a first substrate bias voltage generator, which can be driven by an external clock generator, which also controls further circuits in the integrated circuit, and a second substrate bias voltage generator, characterized in that said second substrate bias voltage generator comprises a substrate bias voltage pump for generating a substrate bias voltage, an integrated oscillator for driving said substrate bias voltage pump, switching means for switching said oscillator on and off, and a comparator circuit for comparing the substrate bias voltage with a reference voltage and providing an output to drive said switching means.
Claim 2
Dependent Claim
99 words
An integrated CMOS circuit comprising a first substrate bias voltage generator, which can be driven by an external clock generator, which also controls further circuits in the integrated circuit, and a second substrate bias voltage generator, characterized in that said second substrate bias voltage generator comprises a substrate bias voltage pump for generating a substrate bias voltage, an integrated oscillator for driving said substrate bias voltage pump, switching means for switching said oscillator on and off, and a comparator circuit for comparing the substrate bias voltage with a reference voltage and providing an output to drive said switching means.
Claim 3
Dependent Claim
38 words
An integrated CMOS circuit as claimed in claim 1, characterized in that the integrated oscillator is a ring oscillator comprising a plurality of series-connected inverter stages, an inverter stage together with the switching means comprising a NOR gate.
Claim 4
Dependent Claim
95 words
An integrated CMOS circuit as claimed in claim 1 or 2, characterized in that the comparator circuit comprises an inverter and a series-connected combination of a PMOS transistor, an NMOS transistor and a second PMOS transistor connected as a diode coupled between the positive supply voltage and the substrate voltage, the first-mentioned PMOS and the NMOS transistor being connected by their gate electrodes to ground, a junction point of their drains being connected to the input of the inverter and the diode-connected second PMOS transistor being connected between the NMOS transistor and the substrate voltage.
Claim 5
Dependent Claim
89 words
An integrated CMOS circuit comprising a substrate and a substrate bias voltage generator, which includes a first junction point and an oscillator having an output, a capacitance coupled between said first junction point and said output, a first NMOS transistor connected as a diode between the first junction point and ground and a second NMOS transistor connected as a diode between the first junction point and the substrate, characterized in that the width/length ratio of the second transistor is substantially larger than the width/length ratio of the first transistor.
Claim 6
Dependent Claim
89 words
An integrated CMOS circuit comprising a substrate and a substrate bias voltage generator, which includes a first junction point and an oscillator having an output, a capacitance coupled between said first junction point and said output, a first NMOS transistor connected as a diode between the first junction point and ground and a second NMOS transistor connected as a diode between the first junction point and the substrate, characterized in that the width/length ratio of the second transistor is substantially larger than the width/length ratio of the first transistor.
Claim 7
Dependent Claim
29 words
An integrated CMOS circuit as claimed in claim 4, characterized in that the width/length ratio of the second transistor exceeds that of the first transistor by a factor 5.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-10 | 1992-10-10 | 1993-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-10 | 1996-10-10 | 1997-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-10 | 2000-10-10 | 2001-04-11 | $7700.00 | Window Closed / Lapsed |