Dielectrically isolated SiC mosfet

Abstract

Abstract A metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising a carrier wafer and a silicon gate region disposed on the carrier wafer. A source region and a drain region made from 3C-silicon carbide are disposed on the carrier wafer above the gate region. A gate oxide, derived from silicon, separates the source and drain regions from the gate region. Laterally oriented oxide trenches separate and dielectrically isolate the MOSFET device from other devices on the carrier wafer. Further, the MOSFET device described above is manufactured in a method comprising the steps of providing a carrier wafer having an oxide layer formed on a surface thereof. A layer of silicon having a given level of conductivity is bonded to the oxide layer of the carrier wafer. Selected portions of the layer of silicon are oxidized to create a plurality of dielectrically isolated silicon islands, one of which forms a gate region. A layer of silicon dioxide is then formed over the dielectrically isolated islands of silicon. Two layers of silicon carbide are then bonded to the layer of silicon dioxide. A source region and a drain region are each formed from the layers of silicon carbide. Selected portions of one of the two layers of silicon carbide are oxidized to dielectrically isolate the source region and the drain region from other semiconductor devices located on the carrier wafer.

Inventors

• 👤 Anthony D. Kurtz
• 👤 Andrew V. Bemis

Bibliographic Details