Method for fabrication of CMOS devices having minimized drain contact area

Claim 1

A method for the fabrication of a semiconductor device, comprising the steps of: forming a trench for well isolation in a predetermined area of a semiconductor substrate; filling said trench for well isolation with an insulating film, completely; forming an N-well and a P-well in the semiconductor substrate, said trench for well isolation being between said N-well and said P-well; forming a gate oxide and a gate electrode on the N-well and on the P-well, in sequence; forming a P + type source and a P + type drain in said N-well and an N + type source an N + type drain in said P-well, said P + type and N + type drains being adjacent to said trench; forming a blanket interlayer insulating layer over the resulting structure; etching said interlayer insulating layer and a portion of said insulating film filled in said trench by use of a contact mask, to form a contact hole which exposes a side of said interlayer insulating layer, said P + type and N + type drains adjacent to said trench and an upper side wall of said trench; and forming a conductive wire in said contact hole, to interconnect said P + type and N + type drains adjacent to said trench with each other.

Claim 2

A method for the fabrication of a semiconductor device, comprising the steps of: forming a trench for well isolation in a predetermined area of a semiconductor substrate; filling said trench for well isolation with an insulating film, completely; forming an N-well and a P-well in the semiconductor substrate, said trench for well isolation being between said N-well and said P-well; forming a gate oxide and a gate electrode on the N-well and on the P-well, in sequence; forming a P + type source and a P + type drain in said N-well and an N + type source an N + type drain in said P-well, said P + type and N + type drains being adjacent to said trench; forming a blanket interlayer insulating layer over the resulting structure; etching said interlayer insulating layer and a portion of said insulating film filled in said trench by use of a contact mask, to form a contact hole which exposes a side of said interlayer insulating layer, said P + type and N + type drains adjacent to said trench and an upper side wall of said trench; and forming a conductive wire in said contact hole, to interconnect said P + type and N + type drains adjacent to said trench with each other.

Claim 3

A method for the fabrication of a semiconductor device comprising the steps of: forming a trench for well isolation in a predetermined area of a semiconductor substrate; filling said trench for well isolation with an insulating film, completely; forming an N-well and a P-well in the semiconductor substrate, said trench for well isolation being between said N-well and said P-well; forming a gate oxide and a gate electrode on the N-well and on the P-well, in sequence; forming a P + type source and a P + type drain in said N-well and an N + type source and an N + type drain in said P-well, said P + type and N + type drains being adjacent to said trench; forming a blanket interlayer insulating layer over the resulting structure; forming a contact mask on said interlayer insulating layer; etching said interlayer insulating layer exposed by said contact mask and a portion of said insulating film filled in said trench being beneath said interlayer insulating layer, to form a contact hole which exposes said P + type and N + type drains adjacent to said trench and upper side walls of said P-well and N-well in said trench; removing said contact mask; implanting P + impurities and N + impurities into exposed areas of said N-well and said P-well in said trench, respectively, to extend said P type and said N type drains; and forming a conductive wire in said contact hole, to interconnect said P + type and N + type drains adjacent to said trench with each other.

Claim 4

A method for the fabrication of a semiconductor device comprising the steps of: forming a trench for well isolation in a predetermined area of a semiconductor substrate; filling said trench for well isolation with an insulating film, completely; forming an N-well and a P-well in the semiconductor substrate, said trench for well isolation being between said N-well and said P-well; forming a gate oxide and a gate electrode on the N-well and on the P-well, in sequence; forming a P + type source and a P + type drain in said N-well and an N + type source and an N + type drain in said P-well, said P + type and N + type drains being adjacent to said trench; forming a blanket interlayer insulating layer over the resulting structure; forming a contact mask on said interlayer insulating layer; etching said interlayer insulating layer exposed by said contact mask and a portion of said insulating film filled in said trench being beneath said interlayer insulating layer, to form a contact hole which exposes said P + type and N + type drains adjacent to said trench and upper side walls of said P-well and N-well in said trench; removing said contact mask; implanting P + impurities and N + impurities into exposed areas of said N-well and said P-well in said trench, respectively, to extend said P type and said N type drains; and forming a conductive wire in said contact hole, to interconnect said P + type and N + type drains adjacent to said trench with each other.