High speed, low power pipelined logic circuit

Claim 2

A complementary pipelined logic circuit, comprising: a voltage supply node, an N-channel pass-gate logic unit having a plurality of pairs of complementary inputs and producing a pair of complementary outputs with a predetermined voltage swing, a load circuit connected to said voltage supply node to establish a pair of complementary logic outputs with a voltage swing greater than the output voltage swing of said logic unit, a control circuit interfacing between said logic unit and said load circuit, said control circuit having a clock input and operating in response to a clock signal applied to said clock input to control the logic states of said load circuit logic outputs in accordance with the logic states of said logic unit outputs, and a pair of inverters connected to respective ones of said load circuit complementary logic outputs, with a HI logic state at one of said logic outputs substantially inhibiting the flow of static current through its associated inverter, said inverters producing outputs suitable for direct application to the inputs of another logic circuit with a pass-gate architecture.

Claim 3

The circuit of claim 1, wherein said load circuit is configured to establish a HI logic output at substantially the supply node voltage.

Claim 4

The circuit of claim 1, said load circuit comprising a regenerative latching circuit.

Claim 5

The circuit of claim 3, said load circuit comprising a pair of P-channel transistors having source-drain circuits connected between said voltage supply node and respective logic outputs, and cross-coupled gates.

Claim 6

The circuit of claim 4, said control circuit comprising a pair of N-channel transistors having source-drain circuits connected between respective load circuit logic outputs and respective outputs from said logic unit, and gates connected to said clock input.

Claim 7

A complementary pipelined logic circuit, comprising: a voltage supply node, an N-channel pass-gate complementary logic unit having a plurality of pairs of complementary inputs and producing a pair of complementary outputs at voltage levels less than the voltage of said supply node, a load circuit connected to said voltage supply node and establishing complementary logic outputs at substantially the voltage of said supply node and at a LO voltage level, respectively, a voltage drop switching circuit having a clock input and connected to alternately connect and disconnect, under the control of a clock signal applied to said logic input, the outputs of said logic unit with respective load circuit logic outputs, said switching circuit maintaining the voltage level of the HI logic unit output at a predetermined voltage drop below the voltage of the load circuit logic output to which it is connected, and a pair of inverters connected to respective ones of said complementary logic outputs, with a HI logic state at one of said logic outputs substantially inhibiting the flow of static current through its associated inverter, said inverters producing outputs suitable for direct application to the inputs of another logic circuit with a pass-gate architecture.

Claim 8

A complementary pipelined logic circuit, comprising: a voltage supply node, an N-channel pass-gate complementary logic unit having a plurality of pairs of complementary inputs and producing a pair of complementary outputs at voltage levels less than the voltage of said supply node, a load circuit connected to said voltage supply node and establishing complementary logic outputs at substantially the voltage of said supply node and at a LO voltage level, respectively, a voltage drop switching circuit having a clock input and connected to alternately connect and disconnect, under the control of a clock signal applied to said logic input, the outputs of said logic unit with respective load circuit logic outputs, said switching circuit maintaining the voltage level of the HI logic unit output at a predetermined voltage drop below the voltage of the load circuit logic output to which it is connected, and a pair of inverters connected to respective ones of said complementary logic outputs, with a HI logic state at one of said logic outputs substantially inhibiting the flow of static current through its associated inverter, said inverters producing outputs suitable for direct application to the inputs of another logic circuit with a pass-gate architecture.

Claim 9

The circuit of claim 6, said load circuit comprising regenerative latching circuit.

Claim 10

The circuit of claim 7, said load circuit comprising a pair of P-channel transistors having source-drain circuits connected between said voltage supply node and respective logic outputs, and cross-coupled gates.

Claim 11

The circuit of claim 8, said switching circuit comprising a pair of N-channel transistors having source-drain circuits connected between respective load circuit logic outputs and respective outputs from said logic unit, and gates connected to said clock input.