US5384493A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hi-speed and low-power flip-flop
Assignee: NEC Corp
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Filing: 1992-10-05
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Granted: 1995-01-24
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Expires: 2012-10-05
Abstract
Abstract A semiconductor integrated circuit comprises a pair of complementary groups of MOS transistors disposed between first and second reference potentials and switched on and off through a pair of complementary groups of input signals inputted to gates thereof, a first switching transistor switched on and off by a clock signal, and a pair of cross-connected second switching transistors disposed between the reference potentials and connected with the pair of groups of MOS transistors. With this construction, unlike prior art techniques, the semiconductor integrated circuit of the present invention operates with greater speed and reduced power consumption, without increasing the channel width of the constituent transistor, and without the need for an inverted clock signal.
Inventors
- 👤 Katsuya Furuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:57
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356121; H03K19/00; H03K19/0008; H03K19/0016; H03K19/02; H03K19/173; H03K19/1733; H03K19/1738; H03K3/356017; H03K3/356026; H03K3/356052; H03K3/35606
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
203 words
A semiconductor integrated circuit comprising: first and second cross-coupled transistors each having its source/drain path connected to a first voltage potential; a first logical circuit section for receiving at least a first input signal, the first logical circuit section being connected to a second voltage potential; a second logical circuit section for receiving at least a second input signal complementary to the first input signal, the second logical circuit section being connected to the second voltage potential; a third transistor having its source/drain path connected between the source/drain path of the first transistor and the first logical circuit section and having a gate terminal for receiving a first clock signal; a fourth transistor having its source/drain path connected between the source/drain path of the second transistor and the second logical circuit section and having a gate terminal for receiving a second clock signal; a first output connected to a node between the source/drain path of the first transistor and the source/drain path of the third transistor for outputting a first output signal; and a second output node connected to a node between the source/drain path of the second transistor and the source/drain path of the fourth transistor for outputting a second output signal.
Claim 2
Dependent Claim
203 words
A semiconductor integrated circuit comprising: first and second cross-coupled transistors each having its source/drain path connected to a first voltage potential; a first logical circuit section for receiving at least a first input signal, the first logical circuit section being connected to a second voltage potential; a second logical circuit section for receiving at least a second input signal complementary to the first input signal, the second logical circuit section being connected to the second voltage potential; a third transistor having its source/drain path connected between the source/drain path of the first transistor and the first logical circuit section and having a gate terminal for receiving a first clock signal; a fourth transistor having its source/drain path connected between the source/drain path of the second transistor and the second logical circuit section and having a gate terminal for receiving a second clock signal; a first output connected to a node between the source/drain path of the first transistor and the source/drain path of the third transistor for outputting a first output signal; and a second output node connected to a node between the source/drain path of the second transistor and the source/drain path of the fourth transistor for outputting a second output signal.
Claim 3
Dependent Claim
39 words
The semiconductor integrated circuit of claim 1 wherein said first and second transistors are P channel type MOS transistors, said third and fourth transistors are N channel type MOS transistors, and said second voltage potential is a ground potential.
Claim 4
Dependent Claim
39 words
The semiconductor integrated circuit of claim 1 wherein said first and second transistors are N channel type MOS transistors, said third and fourth transistors are P channel type MOS transistors, and said first voltage potential is a ground potential.
Claim 5
Dependent Claim
413 words
A semiconductor integrated circuit comprising a first portion and a second portion, (a) the first portion comprising: first and second cross-coupled transistors each having its source/drain path connected to a first voltage potential; a first logical circuit section for receiving at least a first input signal, the first logical circuit section being connected to a second voltage potential; a second logical circuit section for receiving at least a second input signal complementary to the first input signal, the second logical circuit section being connected to the second voltage potential; a third transistor having its source/drain path connected between the source/drain path of the first transistor and the first logical circuit section and having a gate terminal for receiving a first clock signal; a fourth transistor having its source/drain path connected between the source/drain path of the second transistor and the second logical circuit section and having a gate terminal for receiving a second clock signal; a first output connected to a node between the source/drain path of the first transistor and the source/drain path of the third transistor for outputting a first output signal; and a second output node connected to a node between the source/drain path of the second transistor and the source/drain path of the fourth transistor for outputting a second output signal, and (b) the second portion comprising: fifth and sixth cross-coupled transistors each having its source/drain path connected to a third voltage potential; a third logical circuit section for receiving at least the first output signal, the third logical circuit section being connected to a fourth voltage potential; a fourth logical circuit section for receiving at least the second output signal, the fourth logical circuit section being connected to the fourth voltage potential; a seventh transistor having its source/drain path connected between the source/drain path of the fifth transistor and the third logical circuit section and having a gate terminal for receiving a third clock signal; an eighth transistor having its source/drain path connected between the source/drain path of the sixth transistor and the fourth logical circuit section and having a gate terminal for receiving a fourth clock signal; a third output connected to a node between the source/drain path of the fifth transistor and the source/drain path of the seventh transistor for outputting a third output signal; and a fourth output node connected to a node between the source/drain path of the sixth transistor and the source/drain path of the eighth transistor for outputting a fourth output signal.
Claim 6
Dependent Claim
413 words
A semiconductor integrated circuit comprising a first portion and a second portion, (a) the first portion comprising: first and second cross-coupled transistors each having its source/drain path connected to a first voltage potential; a first logical circuit section for receiving at least a first input signal, the first logical circuit section being connected to a second voltage potential; a second logical circuit section for receiving at least a second input signal complementary to the first input signal, the second logical circuit section being connected to the second voltage potential; a third transistor having its source/drain path connected between the source/drain path of the first transistor and the first logical circuit section and having a gate terminal for receiving a first clock signal; a fourth transistor having its source/drain path connected between the source/drain path of the second transistor and the second logical circuit section and having a gate terminal for receiving a second clock signal; a first output connected to a node between the source/drain path of the first transistor and the source/drain path of the third transistor for outputting a first output signal; and a second output node connected to a node between the source/drain path of the second transistor and the source/drain path of the fourth transistor for outputting a second output signal, and (b) the second portion comprising: fifth and sixth cross-coupled transistors each having its source/drain path connected to a third voltage potential; a third logical circuit section for receiving at least the first output signal, the third logical circuit section being connected to a fourth voltage potential; a fourth logical circuit section for receiving at least the second output signal, the fourth logical circuit section being connected to the fourth voltage potential; a seventh transistor having its source/drain path connected between the source/drain path of the fifth transistor and the third logical circuit section and having a gate terminal for receiving a third clock signal; an eighth transistor having its source/drain path connected between the source/drain path of the sixth transistor and the fourth logical circuit section and having a gate terminal for receiving a fourth clock signal; a third output connected to a node between the source/drain path of the fifth transistor and the source/drain path of the seventh transistor for outputting a third output signal; and a fourth output node connected to a node between the source/drain path of the sixth transistor and the source/drain path of the eighth transistor for outputting a fourth output signal.
Claim 7
Dependent Claim
104 words
The semiconductor integrated circuit of claim 4 wherein said first and second logical circuit sections each comprise at least one N channel type MOS transistor having a gate terminal for receiving said first and second input signals, respectively, said third and fourth logical circuit sections each comprise at least one N channel type MOS transistor having a gate terminal for receiving said first and second output signals, respectively, said first, second, fifth, and sixth transistors are P channel type MOS transistors, said third, fourth, seventh, and eighth transistors are N channel type MOS transistors, and said second and fourth voltage potentials are ground potentials.
Claim 8
Dependent Claim
104 words
The semiconductor integrated circuit of claim 4 wherein said first and second logical circuit sections each comprise at least one P channel type MOS transistor having a gate terminal for receiving said first and second input signals, respectively, said third and fourth logical circuit sections each comprise at least one N channel type MOS transistor having a gate terminal for receiving said first and second output signals, respectively, said first, second, seventh, and eighth transistors are N channel type MOS transistors said third, fourth, fifth, and sixth transistors are P channel type MOS transistors, and said first and fourth voltage potentials are ground potentials.
Claim 9
Dependent Claim
20 words
The semiconductor integrated circuit of claim 1 wherein said first and second clock signals are in phase with each other.
Claim 10
Dependent Claim
20 words
The semiconductor integrated circuit of claim 1 wherein said first and second clock signals have phases complementary to each other.
Claim 11
Dependent Claim
20 words
The semiconductor integrated circuit of claim 2 wherein said first and second clock signals are in phase with each other.
Claim 12
Dependent Claim
20 words
The semiconductor integrated circuit of claim 3 wherein said first and second clock signals are in phase with each other.
Claim 13
Dependent Claim
20 words
The semiconductor integrated circuit of claim 2 wherein said first and second clock signals have phases complementary to each other.
Claim 14
Dependent Claim
20 words
The semiconductor integrated circuit of claim 3 wherein said first and second clock signals have phases complementary to each other.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |