US5567553A
Expired / Lapsed
US
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Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures
Assignee: International Business Machines Corp
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Filing: 1995-05-18
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Granted: 1996-10-22
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Expires: 2015-05-18
Abstract
Abstract A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V t , at the shallow trench edges is substantially equal to V t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.
Inventors
- 👤 Louis L. Hsu
- 👤 Chang-Ming Hsieh
- 👤 Lyndon R. Logan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/60; H10D30/611; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
166 words
A method of fabricating a mask used in manufacturing an FET device isolated by shallow trench isolation having a channel width between first and second shallow trenches at first and second shallow trench edges, in which a gate extends across said channel width between said first and second shallow trenches, said gate having both a first length at said shallow trench edges and a second length less than said first length between said shallow trench edges, said method comprising the steps of: forming two opaque stripes on a transparent substrate, said opaque stripes being positioned so that their shadows will overlie said shallow trench edges; depositing a transparent film over the transparent substrate having the opaque stripes deposited theron; forming phase shift patterns in the transparent film, said phase shift pattern extending over portions of said opaque stripes and a region of said transparent substrate; and using the phase shift patterns as a mask to trim exposed portions of said opaque stripes on the transparent substrate.
Claim 2
Independent Claim
166 words
A method of fabricating a mask used in manufacturing an FET device isolated by shallow trench isolation having a channel width between first and second shallow trenches at first and second shallow trench edges, in which a gate extends across said channel width between said first and second shallow trenches, said gate having both a first length at said shallow trench edges and a second length less than said first length between said shallow trench edges, said method comprising the steps of: forming two opaque stripes on a transparent substrate, said opaque stripes being positioned so that their shadows will overlie said shallow trench edges; depositing a transparent film over the transparent substrate having the opaque stripes deposited theron; forming phase shift patterns in the transparent film, said phase shift pattern extending over portions of said opaque stripes and a region of said transparent substrate; and using the phase shift patterns as a mask to trim exposed portions of said opaque stripes on the transparent substrate.
Claim 3
Dependent Claim
25 words
The method of fabricating a mask as recited in claim 1 further comprising the step of selecting said opaque stripes to be formed from chromium.
Claim 4
Dependent Claim
24 words
The method of fabricating a mask as recited in claim 1 further comprising the step of selecting said transparent film to be silicon dioxide.
Claim 5
Dependent Claim
25 words
The method of fabricating a mask as recited in claim 3 further comprising the step of depositing said transparent film by blanket chemical vapor deposition.
Claim 6
Dependent Claim
37 words
The method of fabricating a mask as recited in claim 1 wherein said transparent film is deposited to a thickness sufficient to produce a 180° phase shift at edges of the phase shift patterns during lithographic exposure.
Claim 7
Dependent Claim
23 words
The method of fabricating a mask as recited in claim 1 wherein said phase shift patterns are formed by reactive ion etching (RIE).
Claim 8
Dependent Claim
143 words
A phase shift mask for manufacturing an FET device isolated by shallow trench isolation having a channel width between first and a second shallow trenches at first and second shallow trench edges, in which a gate extends across said channel width between said first and second shallow trenches, said gate having a first length at said shallow trench edges and a second length less than said first length between said shallow trench edges, said mask comprising: a transparent substrate; opaque stripes on said transparent substrate positioned so that their shadows will overlie said shallow trench edges; and a transparent phase shift pattern extending between and overlying said opaque stripes, said opaque stripes being trimmed to the edges of said phase shift pattern and defining said first length and an edge of said transparent phase shift pattern defining said second length of said gate.
Claim 9
Dependent Claim
143 words
A phase shift mask for manufacturing an FET device isolated by shallow trench isolation having a channel width between first and a second shallow trenches at first and second shallow trench edges, in which a gate extends across said channel width between said first and second shallow trenches, said gate having a first length at said shallow trench edges and a second length less than said first length between said shallow trench edges, said mask comprising: a transparent substrate; opaque stripes on said transparent substrate positioned so that their shadows will overlie said shallow trench edges; and a transparent phase shift pattern extending between and overlying said opaque stripes, said opaque stripes being trimmed to the edges of said phase shift pattern and defining said first length and an edge of said transparent phase shift pattern defining said second length of said gate.
Claim 10
Dependent Claim
16 words
The phase shift mask recited in claim 7 wherein said opaque stripes are made of chrome.
Claim 11
Dependent Claim
19 words
The phase shift mask recited in claim 7 wherein said transparent phase shift pattern is made of silicon dioxide.
Claim 12
Dependent Claim
34 words
The phase shift mask recited in claim 7 wherein said transparent phase shift pattern is sufficient to produce a 180° phase shift for lithography exposure at said edge of the transparent phase shift pattern.
Claim 13
Dependent Claim
16 words
The phase shift mask recited in claim 7 wherein said transparent substrate is a quartz plate.
Claim 14
Independent Claim
216 words
A method of manufacturing an FET device isolated by shallow trench isolation having a channel width between first and a second shallow trenches at first and second shallow trench edges, in which a gate extends across said channel width between said first and second shallow trenches, said gate having a first length at said shallow trench edges and a second length less than said first length between said shallow trench edges, said method comprising the steps of: (a) providing a mask having a transparent substrate, opaque stripes on said transparent substrate positioned so that their shadows will overlie said shallow trench edges, and a transparent phase shift pattern extending between and overlying said opaque stripes, said opaque stripes being trimmed to the edges of said phase shift pattern and defining said first length and an edge of said transparent phase shift pattern defining said second length of said gate; and (b) exposing a resist on a silicon wafer with light passing through said mask to form a gate structure of the FET device, said gate structure having a first length at said shallow trench edges defined by said opaque stripes and a second length less than said first length defined by a phase shift of light produced by said edge of said transparent phase shift pattern.
Claim 15
Independent Claim
216 words
A method of manufacturing an FET device isolated by shallow trench isolation having a channel width between first and a second shallow trenches at first and second shallow trench edges, in which a gate extends across said channel width between said first and second shallow trenches, said gate having a first length at said shallow trench edges and a second length less than said first length between said shallow trench edges, said method comprising the steps of: (a) providing a mask having a transparent substrate, opaque stripes on said transparent substrate positioned so that their shadows will overlie said shallow trench edges, and a transparent phase shift pattern extending between and overlying said opaque stripes, said opaque stripes being trimmed to the edges of said phase shift pattern and defining said first length and an edge of said transparent phase shift pattern defining said second length of said gate; and (b) exposing a resist on a silicon wafer with light passing through said mask to form a gate structure of the FET device, said gate structure having a first length at said shallow trench edges defined by said opaque stripes and a second length less than said first length defined by a phase shift of light produced by said edge of said transparent phase shift pattern.
Claim 16
Dependent Claim
60 words
The method recited in claim 12 wherein the transparent phase shift pattern mask defines two gate structures extending between said first and second shallow trenches, said method further comprising the steps of: (c) applying a block out mask between the two gate structures; and (d) etching the pattern area of the block out mask to separate the two gate structures.
Claim 17
Dependent Claim
32 words
The method recited in claim 12 wherein the transparent phase shift pattern mask defines two gate structures extending between said first and second shallow trenches, thereby forming a two gate FET device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |