US5330879A
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Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer
Assignee: Micron Technology Inc
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Filing: 1992-07-16
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Granted: 1994-07-19
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Expires: 2012-07-16
Abstract
Abstract A method for fabricating submicron lines over a semiconductor material by creating a narrow hard mask over the material using a narrow void-producing process. The narrow void is thus used as a mask to form lines that are narrower than those that can be produced by current lithography techniques. The method can also be used to create sharp emission tips for field effect display devices.
Inventors
- 👤 Charles H. Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:16
CPC Classifications
G; G03; G03F; G03F7/00; H; H01; H01J; H01J9/00; H01J9/02; H01J9/022; H01J9/025; H10; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
180 words
A method for fabricating close-tolerance submicron lines on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material; g. anisotropically etching by a photolithography process, the first layer and non-conformal material thereby forming the submicron line below the conformal mask material.
Claim 2
Independent Claim
180 words
A method for fabricating close-tolerance submicron lines on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material; g. anisotropically etching by a photolithography process, the first layer and non-conformal material thereby forming the submicron line below the conformal mask material.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein the loose-tolerance trench is between 0.40 μm and 0.7 μm.
Claim 4
Dependent Claim
13 words
The method of claim 1 wherein the first layer is a mask oxide.
Claim 5
Dependent Claim
21 words
The method of claim 1 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
Claim 6
Dependent Claim
12 words
The method of claim 1 wherein the conformal mask material is polysilicon.
Claim 7
Dependent Claim
17 words
The method of claim 2 wherein the width of the submicron line is less than 0.15 μm.
Claim 8
Independent Claim
188 words
A method for fabricating close-tolerance, sharp emission tip on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance trench in the first layer having a diameter of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material; g. isotropically etching by a photolithography process the first layer and non-conformal material thereby forming the sharp emission tip below the conformal mask material having a lesser diameter than the loose-tolerance well.
Claim 9
Independent Claim
188 words
A method for fabricating close-tolerance, sharp emission tip on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance trench in the first layer having a diameter of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material; g. isotropically etching by a photolithography process the first layer and non-conformal material thereby forming the sharp emission tip below the conformal mask material having a lesser diameter than the loose-tolerance well.
Claim 10
Dependent Claim
17 words
The method of claim 7 wherein the loose-tolerance well is between 0.40 μm and 0.7 μm diameter.
Claim 11
Dependent Claim
13 words
The method of claim 7 wherein the first layer is a mask oxide.
Claim 12
Dependent Claim
21 words
The method of claim 7 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
Claim 13
Dependent Claim
12 words
The method of claim 7 wherein the conformal mask material is polysilicon.
Claim 14
Dependent Claim
18 words
The method of claim 8 wherein the diameter of the sharp emission tip is less than 0.15 μm.
Claim 15
Independent Claim
158 words
A method for fabricating close-tolerance mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; and then f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material.
Claim 16
Independent Claim
158 words
A method for fabricating close-tolerance mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance trench in the first layer having a width of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the trench, said teardrop-shaped void having a narrow, close-tolerance uniform width dimension; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; and then f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the narrow void filled with conformal mask material.
Claim 17
Dependent Claim
16 words
The method of claim 13 wherein the loose-tolerance trench is between 0.40 μm and 0.7 μm.
Claim 18
Dependent Claim
13 words
The method of claim 13 wherein the first layer is a mask oxide.
Claim 19
Dependent Claim
21 words
The method of claim 13 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
Claim 20
Dependent Claim
12 words
The method of claim 13 wherein the conformal mask material is polysilicon.
Claim 21
Dependent Claim
16 words
The method of claim 14 wherein the width of the mask is less than 0.15 μm.
Claim 22
Independent Claim
157 words
A method for fabricating close-tolerance, circular mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance well in the first layer having a width of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the well, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; and then f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material.
Claim 23
Independent Claim
157 words
A method for fabricating close-tolerance, circular mask on a semiconductor wafer having a gate oxide layer over a substrate and a gate polysilicon layer over the gate oxide, comprising the steps of: a. depositing a first layer on top of the gate polysilicon layer; b. forming a loose-tolerance well in the first layer having a width of less than 1 micrometer (μm); c. depositing a non-conformal material to a predetermined thickness of between 0.3 and 0.45 μm over the first layer thereby forming a teardrop-shaped void in the well, said teardrop-shaped void having a narrow, close-tolerance, uniform diameter; d. chemically, mechanically polishing (CMP) the non-conformal material down to a top surface of the first layer, thereby exposing the void; e. depositing a conformal mask material over the first layer and void; and then f. CMP polishing and removing the conformal mask material down to the first layer, thereby leaving only the void filled with conformal mask material.
Claim 24
Dependent Claim
17 words
The method of claim 19 wherein the loose-tolerance well is between 0.40 μm and 0.7 μm diameter.
Claim 25
Dependent Claim
13 words
The method of claim 19 wherein the first layer is a mask oxide.
Claim 26
Dependent Claim
21 words
The method of claim 19 wherein the non-conformal material is selected from the group consisting of silicon oxide and silicon nitride.
Claim 27
Dependent Claim
12 words
The method of claim 19 wherein the conformal mask material is polysilicon.
References Cited (Backward Citations)
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