Process of forming contacts and vias having tapered sidewall

Claim 2

A process of forming a contact hole having a tapered sidewall in an integrated circuit comprising the steps of: preparing a semiconductor substrate having a gate dielectric and a plurality of polysilicons on the top surface of said substrate and a plurality of doped regions inside the top surface of said substrate; establishing a multi-layer insulating structure above said substrate and said polysilicons, said multi-layer insulating structure having a top insulating layer; forming a photo-resist layer over said multi-layer insulating structure, said photo-resist layer having an opening defining an area for forming said contact hole and the size of said opening being slightly larger than the size of said contact hole; anisotropically etching into said multi-layer insulating structure to remove about one half of the thickness of said multi-layer insulating structure through said opening, and forming a void having a vertical sidewall in said multi-layer insulating structure; removing said photo-resist layer to expose said multi-layer insulating structure; depositing a temporary insulating layer having the same composition as said top insulating layer uniformly over the surface of said multi-layer insulating structure; anisotropically etching said temporary insulating layer to expose the top surface of said multi-layer insulating structure and forming a sidewall spacer having a tapered shape on said vertical sidewall, said spacer being a remaining part of said temporary insulating layer; and anisotropically etching said multi-layer insulating structure and said spacer until said substrate is exposed in said opening and said spacer is removed.

Claim 3

The process of forming a contact hole having a tapered sidewall in an integrated circuit according to claim 1, wherein said multi-layer insulating structure comprises a bottom layer of undoped silicon oxide having a thickness between about 500 and 1500 Angstroms and a top layer of borophosphosilicate glass having a thickness between about 5000 and 12000 Angstroms.

Claim 4

The process of forming a contact hole having a tapered sidewall in an integrated circuit according to claim 1, wherein said temporary insulating layer has a thickness between about 700 and 3000 Angstroms and comprises borophosphosilicate glass.

Claim 5

The process of forming a contact hole having a tapered sidewall in an integrated circuit according to claim 1, wherein the step of anisotropically etching said temporary insulating layer and the following step of anisotropically etching said multi-layer insulating structure as well as said spacer are combined and accomplished in a continuous anisotropically etching process within a same chamber.

Claim 6

A process of forming a metal via having a tapered sidewall in an integrated circuit comprising the steps of: preparing a semiconductor device including a lower multi-layer insulating structure, said lower multi-layer insulating structure having a top surface and a metal layer formed over a part of said top surface; establishing an upper multi-layer insulating structure above said top surface and said metal layer, said multi-layer insulating structure having a top insulating layer; forming a photo-resist layer over said upper multi-layer insulating structure, said photo-resist layer having an opening defining an area for forming said metal via and the size of said opening being slightly larger than the size of said metal via; anisotropically etching into said upper multi-layer insulating structure to remove about one half of the thickness of said upper multi-layer insulating structure through said opening, and forming a void having a vertical sidewall in said upper multi-layer insulating structure; removing said photo-resist layer to expose said upper multi-layer insulating structure; depositing a temporary insulating layer having the same composition as said top insulating layer uniformly over the surface of said upper multi-layer insulating structure; anisotropically etching said temporary insulating layer to expose the top surface of said upper multi-layer insulating structure and forming a sidewall spacer having a tapered shape on said vertical sidewall, said spacer being a remaining part of said temporary insulating layer; and anisotropically etching said upper multi-layer insulating structure and said spacer until said metal layer is exposed in said opening and said spacer is removed.

Claim 7

A process of forming a metal via having a tapered sidewall in an integrated circuit comprising the steps of: preparing a semiconductor device including a lower multi-layer insulating structure, said lower multi-layer insulating structure having a top surface and a metal layer formed over a part of said top surface; establishing an upper multi-layer insulating structure above said top surface and said metal layer, said multi-layer insulating structure having a top insulating layer; forming a photo-resist layer over said upper multi-layer insulating structure, said photo-resist layer having an opening defining an area for forming said metal via and the size of said opening being slightly larger than the size of said metal via; anisotropically etching into said upper multi-layer insulating structure to remove about one half of the thickness of said upper multi-layer insulating structure through said opening, and forming a void having a vertical sidewall in said upper multi-layer insulating structure; removing said photo-resist layer to expose said upper multi-layer insulating structure; depositing a temporary insulating layer having the same composition as said top insulating layer uniformly over the surface of said upper multi-layer insulating structure; anisotropically etching said temporary insulating layer to expose the top surface of said upper multi-layer insulating structure and forming a sidewall spacer having a tapered shape on said vertical sidewall, said spacer being a remaining part of said temporary insulating layer; and anisotropically etching said upper multi-layer insulating structure and said spacer until said metal layer is exposed in said opening and said spacer is removed.

Claim 8

The process of forming a metal via having a tapered sidewall in an integrated circuit according to claim 5, wherein both said lower multi-layer insulating structure and said upper multi-layer insulating structure comprise a lower insulating layer of silicon oxide having a thickness between about 1000 and 3000 Angstroms, a middle insulating layer spin-on-glass having a thickness between about 2000 and 6000 Angstroms, and an upper insulating layer of silicon oxide having a thickness between about 3000 and 9000 Angstroms.

Claim 9

The process of forming a metal via having a tapered sidewall in an integrated circuit according to claim 5, wherein said upper multi-layer insulating structure comprises a lower insulating layer of silicon oxide having a thickness between about 1000 and 3000 Angstroms, a middle insulating layer of spin-on-glass having a thickness between about 2000 and 6000 Angstroms, and an upper insulating layer of silicon oxide having a thickness between about 3000 and 9000 Angstroms; and said lower multilayer insulating structure comprises a lower insulating layer of undoped silicon oxide having a thickness between about 500 and 1500 Angstrom and an upper insulating layer of borophosphosilicate glass having a thickness between about 5000 and 12000 Angstroms.

Claim 10

The process of forming a metal via having a tapered sidewall in an integrated circuit according to claim 5, wherein said temporary insulating layer has a thickness between about 700 and 3000 Angstroms and comprises silicon oxide.

Claim 11

The process of forming a metal via having a tapered sidewall in an integrated circuit according to claim 5, wherein the step of anisotropically etching said temporary insulating layer and the following step of anisotropically etching said upper multi-layer insulating structure as well as said spacer are combined and accomplished in a continuous anisotropically etching process within a same chamber.