US5203957A — Contact sidewall tapering with argon sputtering

Claim 1

Independent Claim 163 words

A method for making a contact opening for an integrated circuit in a horizontal plane having a feature size of about one micrometer or less comprising: providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover; forming a resist masking layer over the said multilayer insulating layer having openings therein in the areas where the said contact openings are desired; isotropic etching through a thickness portion of said multilayer insulating layer; anisotropic etching through the remaining thickness of said multilayer insulating layer to the semiconductor substrate to form said contact opening; removing the said resist layer; and subjecting the structure to an Argon sputter etching ambient that is influenced by a magnetic field that causes preferential etching along a direction that is approximately 45 degrees to the horizontal plane to smooth the sharp corners at the upper surface of said multilayer layer and the point where the said isotropic etching ended and the anisotropic etching began.

Claim 2

Independent Claim 163 words

A method for making a contact opening for an integrated circuit in a horizontal plane having a feature size of about one micrometer or less comprising: providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover; forming a resist masking layer over the said multilayer insulating layer having openings therein in the areas where the said contact openings are desired; isotropic etching through a thickness portion of said multilayer insulating layer; anisotropic etching through the remaining thickness of said multilayer insulating layer to the semiconductor substrate to form said contact opening; removing the said resist layer; and subjecting the structure to an Argon sputter etching ambient that is influenced by a magnetic field that causes preferential etching along a direction that is approximately 45 degrees to the horizontal plane to smooth the sharp corners at the upper surface of said multilayer layer and the point where the said isotropic etching ended and the anisotropic etching began.

Claim 3

Dependent Claim 20 words

The method of claim 1 wherein said multilayer layer is composed of a layer of silicon oxide and borophosphosilicate glass.

Claim 4

Dependent Claim 30 words

The method of claim 2 wherein said borophosphosphosilicate glass thickness in between about 4000 Angstroms and 10,000 Angstroms said silicon oxide thickness is between about 1000 Angstroms and 2000 Angstroms.

Claim 5

Dependent Claim 25 words

The method of claim 3 wherein said isotropic etching is continued to a thickness of about 3000 Angstroms to 4000 Angstroms of said borophosphosilicate glass.

Claim 6

Dependent Claim 49 words

The method of claim 4 wherein said Argon sputter etching continues until from between about 500 to 1250 Angstroms of material is removed during the smoothing step which results in tapering of sharp corners as a result, the metal step coverage is improved from between about 34% to 69%.

Claim 7

Dependent Claim 16 words

The method of claim 1 wherein said integrated circuit includes metal oxide semiconductor field effect transistors.

Claim 8

Dependent Claim 12 words

The method of claim 1 wherein said integrated circuit includes bipolar transistors.

Claim 9

Independent Claim 166 words

A method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less comprising: providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover; forming a resist masking layer over the said multilayer insulating layer having openings therein in the areas where the said contact openings are desired; isotropic etching through a thickness portion of said multilayer insulating layer; anisotropic etching through the remaining thickness of said multilayer insulating layer to the semiconductor substrate to form said contact opening; removing the said resist layer; subjecting the structure to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of said multilayer layer and the point where the said isotropic etching ended and the anisotropic etching began and soft reactive ion etching for a period of less than about 30 seconds after said argon sputter etching to reduce the increased contact resistance caused by this argon sputter etching.

Claim 10

Independent Claim 166 words

A method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less comprising: providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover; forming a resist masking layer over the said multilayer insulating layer having openings therein in the areas where the said contact openings are desired; isotropic etching through a thickness portion of said multilayer insulating layer; anisotropic etching through the remaining thickness of said multilayer insulating layer to the semiconductor substrate to form said contact opening; removing the said resist layer; subjecting the structure to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of said multilayer layer and the point where the said isotropic etching ended and the anisotropic etching began and soft reactive ion etching for a period of less than about 30 seconds after said argon sputter etching to reduce the increased contact resistance caused by this argon sputter etching.

Claim 11

Dependent Claim 16 words

The method of claim 8 wherein said soft etching uses a helium ambient plus reactive gases.

Claim 12

Dependent Claim 12 words

The method of claim 9 wherein the said reactive gases include trifluoromethane.

Claim 13

Dependent Claim 14 words

The method of claim 10 wherein the said reactive gases also include carbon tetrafluoride.

Claim 14

Dependent Claim 194 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, in a horizontal plane, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said silicate glass layer having openings therein in the areas where the said contact openings are desired; isotropic etching through a thickness portion of said silicate glass layer; anisotropic etching through the remaining thickness of said silicate glass layer and said silicon oxide layer to the semiconductor substrate to form said contact openings; removing the said resist layer; and subjecting the structure to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of said silicate glass layer and the point where the said isotropic etching ended and the anisotropic etching began and soft reactive ion etching for a period of less than about 60 seconds after said argon sputter etching to reduce the increased contact resistance caused by this argon sputter etching.

Claim 15

Dependent Claim 194 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, in a horizontal plane, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said silicate glass layer having openings therein in the areas where the said contact openings are desired; isotropic etching through a thickness portion of said silicate glass layer; anisotropic etching through the remaining thickness of said silicate glass layer and said silicon oxide layer to the semiconductor substrate to form said contact openings; removing the said resist layer; and subjecting the structure to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of said silicate glass layer and the point where the said isotropic etching ended and the anisotropic etching began and soft reactive ion etching for a period of less than about 60 seconds after said argon sputter etching to reduce the increased contact resistance caused by this argon sputter etching.

Claim 16

Dependent Claim 40 words

The method of claim 12 wherein said silicate glass layer is composed of a layer borophosphosilicate glass having a thickness of between about 4000 Angstroms and 10000 Angstroms said silicon oxide thickness is between about 1000 Angstroms and 2000 Angstroms.

Claim 17

Dependent Claim 25 words

The method of claim 13 wherein said isotropic etching is continued to a thickness of about 3000 Angstroms to 5000 Angstroms of said borophosphosilicate glass.

Claim 18

Dependent Claim 47 words

The method of claim 14 wherein said Argon sputter etching continues until from between about 500 to 1250 Angstroms of material is removed during the smoothing step which results in tapering of sharp corners and improvement on the metal step to from between about 34% to 69%.

Claim 19

Dependent Claim 22 words

The method of claim 12 wherein said soft reactive ion etching uses a helium ambient plus reactive gases which includes carbon tetrafluoride.

Claim 20

Dependent Claim 12 words

The method of claim 16 wherein the said reactive gases include trifluoromethane.

Claim 21

Dependent Claim 27 words

The method of claim 12 wherein said contact openings are made to a refractory metal silicide layer which in turn in ohmic contact to said device elements.

Claim 22

Dependent Claim 14 words

The method of claim 12 wherein said refractory metal silicide layer is titanium silicide.

Claim 23

Dependent Claim 184 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, in a horizontal plane, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said silicate glass layer having openings therein in the area where the said contact openings are desired; isotropic etching through a thickness portion of said silicate glass layer; anisotropic etching through the remaining thickness of said silicate glass layer and said silicon oxide layer to the semiconductor substrate to form said contact openings; removing the said resist layer; and subjecting the structure to an Argon sputter etching ambient that is influenced by a magnetic field that causes preferential etch in a direction approximately 45 degrees to the horizontal plane, to smooth the sharp corners at the upper surface of said silicate glass layer and the point where the said isotropic etching ended and the anisotropic etching began.

Claim 24

Dependent Claim 184 words

In the method of fabrication of a metal oxide semiconductor field effect integrated circuit having a feature size of about one micrometer or less wherein the semiconductor integrated circuit structure having device elements is covered with a silicon oxide layer and a silicate glass layer, in a horizontal plane, a process for forming tapered contact openings to device elements comprising: forming a resist masking layer over the said silicate glass layer having openings therein in the area where the said contact openings are desired; isotropic etching through a thickness portion of said silicate glass layer; anisotropic etching through the remaining thickness of said silicate glass layer and said silicon oxide layer to the semiconductor substrate to form said contact openings; removing the said resist layer; and subjecting the structure to an Argon sputter etching ambient that is influenced by a magnetic field that causes preferential etch in a direction approximately 45 degrees to the horizontal plane, to smooth the sharp corners at the upper surface of said silicate glass layer and the point where the said isotropic etching ended and the anisotropic etching began.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-04-19	1996-10-19	1997-04-20	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-04-19	2000-10-19	2001-04-20	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-04-19	2004-10-19	2005-04-20	$7700.00	Window Closed / Lapsed

Contact sidewall tapering with argon sputtering

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