Tapering of holes through dielectric layers for forming contacts in integrated devices

Claim 1

A process for forming a tapered hole through a dielectric layer for making an electric contact in an integrated semiconductor device which comprises: a) providing a semiconducting or conducting substrate having a first dielectric layer thereon; b) anisotropically etching in a RIE plasma through a contact mask said first dielectric layer to thereby form a first etch hole having substantially vertical walls and wherein said etching is to a depth less than the thickness of said first dielectric, layer thereby leaving a residual thickness of dielectric material on the bottom of said first etch hole; c) removing the residual material of said contact mask; d) conformally depositing a second layer of dielectric material over said first dielectric layer and over said residual thickness of dielectric material on the bottom of said first etch hole; e) anisotropically etching without masking in a RIE plasma said second layer of dielectric material and said first dielectric layer beneath said second layer until exposing the surface of said semiconducting or conducting substrate at the bottom of the etch hole while leaving on said substantially vertical walls of said first etch hole through a portion of the thickness of said first dielectric layer a tapered residue of dielectric material of said conformally deposited second layer of dielectric material.