Patent US5566303A successfully refreshed from Google Patents.
US5566303A
Expired / Lapsed
US
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Microcomputer with multiple CPU'S on a single chip with provision for testing and emulation of sub CPU's
Assignee: Mitsubishi Electric Corp
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Filing: 1994-05-31
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Granted: 1996-10-15
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Expires: 2014-05-31
Abstract
Abstract A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside.
Inventors
- 👤 Tetsu Tashiro
- 👤 Yoshiki Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:50
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701; G06F11/273; G06F11/2736
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
199 words
A microcomputer having a main CPU capable of accessing a main memory area through a main CPU bus and at least one sub CPU capable of accessing a sub memory area through a sub CPU bus, comprising: a control register which can be accessed from the main CPU, controlling means for connecting said sub memory area to said main CPU bus to make said sub memory area accessible from said main CPU, when said main CPU writes a predetermined value in said control register, program counter which generates an address of an instruction of a program to be executed next; and controlling means for loading a test reset vector indicating a start address of a test program for said sub memory area into said program counter upon reset of said sub CPU from said main CPU, when said main CPU has written a predetermined value in said control register, wherein said controlling means controls loading of an output value of hard logic which is fixed in advance, data written in a ROM which constitutes said sub memory area, or a value written in an exclusive register which is accessible from said main CPU bus, as the test reset vector.
Claim 2
Dependent Claim
199 words
A microcomputer having a main CPU capable of accessing a main memory area through a main CPU bus and at least one sub CPU capable of accessing a sub memory area through a sub CPU bus, comprising: a control register which can be accessed from the main CPU, controlling means for connecting said sub memory area to said main CPU bus to make said sub memory area accessible from said main CPU, when said main CPU writes a predetermined value in said control register, program counter which generates an address of an instruction of a program to be executed next; and controlling means for loading a test reset vector indicating a start address of a test program for said sub memory area into said program counter upon reset of said sub CPU from said main CPU, when said main CPU has written a predetermined value in said control register, wherein said controlling means controls loading of an output value of hard logic which is fixed in advance, data written in a ROM which constitutes said sub memory area, or a value written in an exclusive register which is accessible from said main CPU bus, as the test reset vector.
Claim 3
Dependent Claim
201 words
A microcomputer, comprising: a main CPU capable of accessing a main memory area through a main CPU bus; and at least one sub CPU having a program counter which generates an address of an instruction of a program to be executed next and capable of accessing a sub memory area through a sub CPU bus; further comprising: a break address register which stores a break address for executing another program by interrupting a program under operation; comparing means which always compares the value of said program counter of said sub CPU and the value of said break address register to detect their agreement; and controlling means for loading the break vector as the start address of said another program to said program counter to branch the program by generating a break interrupt when said comparing means detects the agreement of the values, wherein said break address register is accessible from said main CPU through said main CPU bus and is provided with controlling means for loading an output value of a hard logic which is fixed in advance, data written in a ROM which constitute said sub memory area, or a value stored in an exclusive register to said program counter.
Claim 4
Dependent Claim
201 words
A microcomputer, comprising: a main CPU capable of accessing a main memory area through a main CPU bus; and at least one sub CPU having a program counter which generates an address of an instruction of a program to be executed next and capable of accessing a sub memory area through a sub CPU bus; further comprising: a break address register which stores a break address for executing another program by interrupting a program under operation; comparing means which always compares the value of said program counter of said sub CPU and the value of said break address register to detect their agreement; and controlling means for loading the break vector as the start address of said another program to said program counter to branch the program by generating a break interrupt when said comparing means detects the agreement of the values, wherein said break address register is accessible from said main CPU through said main CPU bus and is provided with controlling means for loading an output value of a hard logic which is fixed in advance, data written in a ROM which constitute said sub memory area, or a value stored in an exclusive register to said program counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-15 | 2000-04-15 | 2000-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-15 | 2004-04-15 | 2004-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-15 | 2008-04-15 | 2008-10-15 | $7700.00 | Window Closed / Lapsed |