Bus-to-bus pacing logic for improving information transfers in a multi-bus information handling system

Claim 1

An information handling system for computer system comprising (i) a system bus having a slave memory device attached thereto; and (ii) a host bridge for connecting the system bus to a peripheral bus having a master peripheral device attached thereto, said peripheral bus conforming to Peripheral Component Interconnect (PCI) bus architecture; the master peripheral device capable of controlling the peripheral bus to initiate read operations of read data stored in the slave memory device over the host bridge and write operations of write data to be written to the slave memory device over the host bridge, said information handling system comprising: buffer storage within the host bridge for temporarily storing the read data and the write data; a system bus interface between said buffer storage and the system bus; and a peripheral bus interface between said buffer storage and the peripheral bus, said peripheral bus interface including logic for alternatively, during a single data transfer, (i) asserting a target ready signal to be detected by the master peripheral device when said buffer storage is not full to indicate that said buffer storage may accept data from the master peripheral device during a write operation or to transfer data to the master peripheral device during a read operation; and (ii) deasserting said target ready signal to be detected by the master peripheral device when said buffer storage is full to suspend transfer of data into and out of said buffer storage and to indicate that said buffer storage may not accept data from the master peripheral device during a write operation or to transfer data to the master peripheral device during a read operation, the master peripheral device maintaining control of the peripheral bus while said target ready signal is being asserted and deasserted during said single data transfer.

Claim 8

A method of managing data transfers in a computer system comprising (a) a system bus having a slave memory device attached thereto; and (b) a host bridge for connecting the system bus to a peripheral bus having a master peripheral device attached thereto, said peripheral bus conforming to Peripheral Component Interconnect (PCI) bus architecture; said method comprising the steps of: (i) controlling the peripheral bus with the master peripheral device to initiate read operations of read data stored in the slave memory device over the host bridge and write operations of write data to be written to the slave memory device over the host bridge; (ii) temporarily storing the read data and the write data in buffer storage within the host bridge; alternately, during a single data transfer of said read and write data, (iii)(a) asserting a target ready signal to be detected by the master peripheral device when said buffer storage is not full to indicate that said buffer storage may accept data from the master peripheral device during a write operation or to transfer data to the master peripheral device during a read operation; and (iii) (b) deasserting said target ready signal to be detected by the master peripheral device when said buffer storage is full to suspend transfer of data into and out of said buffer storage and to indicate that said buffer storage may not accept data from the master peripheral device during a write operation or to transfer data to the master peripheral device during a read operation; and (iv) maintaining control of said peripheral bus with said master peripheral device regardless of whether said target ready signal is asserted or deasserted.

Claim 9

A method of managing data transfers in a computer system comprising (a) a system bus having a slave memory device attached thereto; and (b) a host bridge for connecting the system bus to a peripheral bus having a master peripheral device attached thereto, said peripheral bus conforming to Peripheral Component Interconnect (PCI) bus architecture; said method comprising the steps of: (i) controlling the peripheral bus with the master peripheral device to initiate read operations of read data stored in the slave memory device over the host bridge and write operations of write data to be written to the slave memory device over the host bridge; (ii) temporarily storing the read data and the write data in buffer storage within the host bridge; alternately, during a single data transfer of said read and write data, (iii)(a) asserting a target ready signal to be detected by the master peripheral device when said buffer storage is not full to indicate that said buffer storage may accept data from the master peripheral device during a write operation or to transfer data to the master peripheral device during a read operation; and (iii) (b) deasserting said target ready signal to be detected by the master peripheral device when said buffer storage is full to suspend transfer of data into and out of said buffer storage and to indicate that said buffer storage may not accept data from the master peripheral device during a write operation or to transfer data to the master peripheral device during a read operation; and (iv) maintaining control of said peripheral bus with said master peripheral device regardless of whether said target ready signal is asserted or deasserted.