High speed IEEE 488 bus interface system and method

Claim 2

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; and source handshake means, coupled to said IEEE 488 bus, for asserting a data message, comprising a sequence of data bytes from said first device via said input/output port, onto said data lines of said IEEE 488 bus, and for asserting a data valid signal on said DAV line in coordination with asserting said sequence of data bytes on said data lines of said IEEE 488 bus; said source handshake means including source mode determination means (A) for automatically transmitting via said IEEE 488 bus, to specified acceptor devices coupled to said IEEE 488 bus, a high-speed-capable message that indicates that said bus interface is capable of high speed data transmissions, and (B) for monitoring said IEEE 488 bus for a predefined response signal indicating whether all of said specified acceptor device have bus interfaces capable of high speed data transmissions; said source handshake means including source handshake state machine means for asserting said data valid signal on said DAV line using a first, low speed, data transmission protocol when said predefined response signal is not detected by said source mode determination means, and for asserting said data valid signal on said DAV line using a second, high speed, data transmission protocol when said predefined response signal is detected by said source mode determination means; wherein said source handshake means automatically determines whether all of said specified acceptor devices have bus interfaces capable of high speed data transmission each time transmission of a data message begins; said source handshake state machine means including first sourcing means for coordinating assertion of said data valid signal on said DAV line with interlock signals received from said specified acceptor devices on said NRFD line and DAC line when using said first, low speed, data transmission protocol, and second sourcing means for asserting and deasserting said data valid signal on said DAV line in a predefined pulsing pattern, so long as (A) said sequence of data bytes are available for transmission, and (B) said interlock signals are not received from said specified acceptor devices on said NRFD line and DAC line, when using said second, high speed, data transmission protocol; said source mode determination means further including means for deactivating said second sourcing means and activating said first sourcing means when any of said specified acceptor devices transmits a terminate-high-speed-mode message via said IEEE 488 bus.

Claim 3

The bus interface of claim 1, said second sourcing means further including means for suspending transmission of further data bytes when any of said specified acceptor devices asserts a predefined suspend-transmission signal on one of said DAC and NRFD lines, and for resuming transmission of said further data bytes when said suspend-transmission signal on said one of said DAC and NRFD lines is deasserted.

Claim 4

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, and a not-ready for data (NRFD) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; and source handshake means, coupled to said IEEE 488 bus, for asserting a data message, comprising a sequence of data bytes from said first device via said input/output port, onto said data lines of said IEEE 488 bus, and for asserting a data valid signal on said DAV line in coordination with asserting said sequence of data bytes on said data lines of said IEEE 488 bus; said source handshake means including source mode determination means (A) for automatically transmitting via said IEEE 488 bus, to specified acceptor devices coupled to said IEEE 488 bus, a high-speed-capable message that indicates that said bus interface is capable of high speed data transmissions, and (B) for monitoring said IEEE 488 bus for a predefined response signal indicating whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions; said source handshake means including source handshake state machine means for asserting said data valid signal on said DAV line using a first, low speed, data transmission protocol when said predefined response signal is not detected by said source mode determination means, and for asserting said data valid signal on said DAV line using a second, high speed, data transmission protocol when said predefined response signal is detected by said source mode determination means; wherein said source handshake means automatically determines whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions each time transmission of a data message begins; said high-speed-capable message transmitted by said source mode determination means comprising a pulse of predefined duration on said NRFD line after asserting data on said data lines but prior to asserting a data valid signal on said DAV line.

Claim 5

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, and a not-ready for data (NRFD) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; and source handshake means, coupled to said IEEE 488 bus, for asserting a data message, comprising a sequence of data bytes from said first device via said input/output port, onto said data lines of said IEEE 488 bus, and for asserting a data valid signal on said DAV line in coordination with asserting said sequence of data bytes on said data lines of said IEEE 488 bus; said source handshake means including source mode determination means (A) for automatically transmitting via said IEEE 488 bus, to specified acceptor devices coupled to said IEEE 488 bus, a high-speed-capable message that indicates that said bus interface is capable of high speed data transmissions, and (B) for monitoring said IEEE 488 bus for a predefined response signal indicating whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions; said source handshake means including source handshake state machine means for asserting said data valid signal on said DAV line using a first, low speed, data transmission protocol when said predefined response signal is not detected by said source mode determination means, and for asserting said data valid signal on said DAV line using a second, high speed, data transmission protocol when said predefined response signal is detected by said source mode determination means; wherein said source handshake means automatically determines whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions each time transmission of a data message begins; said high-speed-capable message transmitted by said source mode determination means comprising a pulse of predefined duration on said NRFD line after asserting data on said data lines but prior to asserting a data valid signal on said DAV line.

Claim 6

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; source handshake means, coupled to said IEEE 488 bus, for asserting a data message, comprising a sequence of data bytes from said first device via said input/output port, onto said data lines of said IEEE 488 bus, and for asserting a data valid signal on said DAV line in coordination with asserting said sequence of data bytes on said data lines of said IEEE 488 bus; said source handshake means including source mode determination means (A) for automatically transmitting via said IEEE 488 bus, to specified acceptor devices coupled to said IEEE 488 bus, a high-speed-capable message that indicates that said bus interface is capable of high speed data transmissions, and (B) for monitoring said IEEE 488 bus for a predefined response signal indicating whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions; said source handshake means including source handshake state machine means for asserting said data valid signal on said DAV line using a first, low speed, data transmission protocol when said predefined response signal is not detected by said source mode determination means, and for asserting said data valid signal on said DAV line using a second, high speed, data transmission protocol when said predefined response signal is detected by said source mode determination means; wherein said source handshake means automatically determines whether all of said specified acceptor devices have bus interfaces capable of high speed data transmission each time transmission of a data message begins; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said first device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether a specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting said interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using said first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has a bus interface capable of high speed data transmissions each time that a new data message is received by said bus interface coupled to said first device.

Claim 7

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; source handshake means, coupled to said IEEE 488 bus, for asserting a data message, comprising a sequence of data bytes from said first device via said input/output port, onto said data lines of said IEEE 488 bus, and for asserting a data valid signal on said DAV line in coordination with asserting said sequence of data bytes on said data lines of said IEEE 488 bus; said source handshake means including source mode determination means (A) for automatically transmitting via said IEEE 488 bus, to specified acceptor devices coupled to said IEEE 488 bus, a high-speed-capable message that indicates that said bus interface is capable of high speed data transmissions, and (B) for monitoring said IEEE 488 bus for a predefined response signal indicating whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions; said source handshake means including source handshake state machine means for asserting said data valid signal on said DAV line using a first, low speed, data transmission protocol when said predefined response signal is not detected by said source mode determination means, and for asserting said data valid signal on said DAV line using a second, high speed, data transmission protocol when said predefined response signal is detected by said source mode determination means; wherein said source handshake means automatically determines whether all of said specified acceptor devices have bus interfaces capable of high speed data transmission each time transmission of a data message begins; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said first device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether a specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting said interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using said first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has a bus interface capable of high speed data transmissions each time that a new data message is received by said bus interface coupled to said first device.

Claim 8

The bus interface of claim 4, said bus interface further including data in buffer means for temporarily storing said data bytes received by said listener circuit means prior to transmission thereof to said first device; said data in buffer means including monitoring means for generating a not-ready signal when said data in buffer means has less than a predefined amount of unused storage capacity; said acceptor handshake means further including means for asserting a predefined suspend-transmission signal on one of said DAC and NRFD lines when said data in buffer means generates said not-ready signal, and for deasserting said suspend-transmission signal on said one of said DAC and NRFD lines when said data in buffer means stops generating said not-ready signal.

Claim 9

The bus interface of claim 5, said acceptor handshake means including means for transmitting a terminate-high-speed-mode message to said specified sourcing device via said IEEE 488 bus, said acceptor handshake state machine means including means for using said first, low speed, data transmission protocol a predefined time interval after transmission of said terminate-high-speed-mode message by said acceptor handshake means.

Claim 10

The bus interface of claim 4, said high-speed-capable message transmitted by said specified source devices comprising a pulse of predefined duration on said NRFD line prior to said acceptor handshake means detecting a data valid signal on said DAV line.

Claim 11

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said first device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether a specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting said interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using a first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has a bus interface capable of high speed data transmissions each time that a new data message is received by said bus interface coupled to said first device; said acceptor handshake means including means for transmitting a terminate-high-speed-mode message to said specified sourcing device via said IEEE 488 bus, said acceptor handshake state machine means including means for using said first, low speed, data transmission protocol a predefined time interval after transmission of said terminate-high-speed-mode message by said acceptor handshake means.

Claim 12

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said first device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether a specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting said interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using a first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has a bus interface capable of high speed data transmissions each time that a new data message is received by said bus interface coupled to said first device; said acceptor handshake means including means for transmitting a terminate-high-speed-mode message to said specified sourcing device via said IEEE 488 bus, said acceptor handshake state machine means including means for using said first, low speed, data transmission protocol a predefined time interval after transmission of said terminate-high-speed-mode message by said acceptor handshake means.

Claim 13

The bus interface of claim 8, said bus interface further including data in buffer means for temporarily storing said data bytes received by said listener circuit means prior to transmission thereof to said first device; said data in buffer means including monitoring means for generating a not-ready signal when said data in buffer means has less than a predefined amount of unused storage capacity; said acceptor handshake means further including means for asserting a predefined suspend-transmission signal on one of said DAC and NRFD lines when said data in buffer means generates said not-ready signal, and for deasserting said suspend-transmission signal on said one of said DAC and NRFD lines when said data in buffer means stops generating said not-ready signal.

Claim 14

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said first device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether a specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using a first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has a bus interface capable of high speed data transmissions each time that a new data message is received by said bus interface coupled to said first device; said high-speed-capable message transmitted by said specified source devices comprising a pulse of predefined duration on said NRFD line prior to said acceptor handshake means detecting a data valid signal on said DAV line.

Claim 15

A bus interface that couples a first device to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; said bus interface comprising: an input/output port which transmits and receives data to and from said first device; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said first device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether a specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using a first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has a bus interface capable of high speed data transmissions each time that a new data message is received by said bus interface coupled to said first device; said high-speed-capable message transmitted by said specified source devices comprising a pulse of predefined duration on said NRFD line prior to said acceptor handshake means detecting a data valid signal on said DAV line.

Claim 16

In a system having a plurality of devices coupled to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; wherein any one said plurality of devices can be specified to be a sourcing device and any other ones of said plurality of devices can be specified to be acceptor devices for purposes of transmitting a data message from the specified sourcing device to the specified acceptor devices; the combination comprising: a first bus interface, associated with a first one of said plurality of devices, that couples said first device to said IEEE 488 bus; said first bus interface including: an input/output port which transmits and receives data to and from said first device; source handshake means, coupled to said IEEE 488 bus, for asserting a data message, comprising a sequence of data bytes from said first device via said input/output port, onto said data lines of said IEEE 488 bus, and for asserting a data valid signal on said DAV line in coordination with asserting said sequence of data bytes on said data lines of said IEEE 488 bus; said source handshake means including source mode determination means (A) for automatically transmitting via said IEEE 488 bus, to said specified acceptor devices coupled to said IEEE 488 bus, a high-speed-capable message that indicates that said bus interface is capable of high speed data transmissions, and (B) for monitoring said IEEE 488 bus for a predefined response signal indicating whether all of said specified acceptor devices have interfaces capable of high speed data transmissions; said source handshake means including source handshake state machine means for asserting said data valid signal on said DAV line using a first, low speed, data transmission protocol when said predefined response signal is not detected by said source mode determination means, and for asserting said data valid signal on said DAV line using a second, high speed, data transmission protocol when said predefined response signal is detected by said source mode determination means; said high-speed-capable message transmitted by said source mode determination means comprising a pulse of predefined duration on said NRFD line after asserting data on said data lines but prior to asserting a data valid signal on said DAV line; wherein said source handshake means automatically determines whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions each time transmission of a data message begins; and a second bus interface, associated with a second one of said plurality of devices, that couples said second device to said IEEE 488 bus; said second bus interface including: an input/output port which transmits and receives data to and from said second device; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said second device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether said specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using said first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has bus interface capable of high speed data transmissions each time that a new data message is received by said second bus interface.

Claim 17

In a system having a plurality of devices coupled to an IEEE 488 bus, said IEEE 488 bus including data lines, a data valid (DAV) line, a not-ready for data (NRFD) line, and a data accepted (DAC) line; wherein any one said plurality of devices can be specified to be a sourcing device and any other ones of said plurality of devices can be specified to be acceptor devices for purposes of transmitting a data message from the specified sourcing device to the specified acceptor devices; the combination comprising: a first bus interface, associated with a first one of said plurality of devices, that couples said first device to said IEEE 488 bus; said first bus interface including: an input/output port which transmits and receives data to and from said first device; source handshake means, coupled to said IEEE 488 bus, for asserting a data message, comprising a sequence of data bytes from said first device via said input/output port, onto said data lines of said IEEE 488 bus, and for asserting a data valid signal on said DAV line in coordination with asserting said sequence of data bytes on said data lines of said IEEE 488 bus; said source handshake means including source mode determination means (A) for automatically transmitting via said IEEE 488 bus, to said specified acceptor devices coupled to said IEEE 488 bus, a high-speed-capable message that indicates that said bus interface is capable of high speed data transmissions, and (B) for monitoring said IEEE 488 bus for a predefined response signal indicating whether all of said specified acceptor devices have interfaces capable of high speed data transmissions; said source handshake means including source handshake state machine means for asserting said data valid signal on said DAV line using a first, low speed, data transmission protocol when said predefined response signal is not detected by said source mode determination means, and for asserting said data valid signal on said DAV line using a second, high speed, data transmission protocol when said predefined response signal is detected by said source mode determination means; said high-speed-capable message transmitted by said source mode determination means comprising a pulse of predefined duration on said NRFD line after asserting data on said data lines but prior to asserting a data valid signal on said DAV line; wherein said source handshake means automatically determines whether all of said specified acceptor devices have bus interfaces capable of high speed data transmissions each time transmission of a data message begins; and a second bus interface, associated with a second one of said plurality of devices, that couples said second device to said IEEE 488 bus; said second bus interface including: an input/output port which transmits and receives data to and from said second device; listener circuit means, coupled to said input/output port and said IEEE 488 bus, for receiving a data message, comprising a sequence of data bytes, from said data lines of said IEEE 488 bus and transmitting said received sequence of data bytes to said second device via said input/output port; and acceptor handshake means, coupled to said listener circuit means and said IEEE 488 bus, for monitoring said DAV line to detect data valid signals thereon, and for coordinating reception of said sequence of data bytes from said data lines of said IEEE 488 bus with said data valid signals on said DAV line; said acceptor handshake means including acceptor mode determination means for automatically monitoring said IEEE 488 bus to determine whether said specified sourcing device coupled to said IEEE 488 bus transmits said high-speed-capable message indicating that said specified sourcing device is capable of high speed data transmissions; said acceptor handshake means including acceptor handshake state machine means (A) for asserting interlock signals on said NRFD and DAC lines in coordination with said data valid signal on said DAV line for each said received data byte using said first, low speed, data transmission protocol when said high-speed-capable message is not detected by said acceptor mode determination means, and (B) for suppressing assertion of said interlock signals on said NRFD and DAC lines using said second, high speed, data transmission protocol when said high-speed-capable message is detected by said acceptor mode determination means; wherein said acceptor handshake means automatically determines whether said specified sourcing device has bus interface capable of high speed data transmissions each time that a new data message is received by said second bus interface.

Claim 18

The combination of claim 11, said first bus interface having means for enabling said source handshake means only when said first device is said specified sourcing device; and said second bus interface having means for enabling said acceptor handshake means only when said second device is one of said specified acceptor devices.

Claim 19

The combination of claim 11, said source handshake state machine means including first sourcing means for coordinating assertion of said data valid signal on said DAV line with interlock signals received from said specified acceptor devices on said NRFD line and DAC line when using said first, low speed, data transmission protocol, and second sourcing means for asserting and deasserting said data valid signal on said DAV line in a predefined pulsing pattern, so long as (A) said sequence of data bytes are available for transmission, and (B) said interlock signals are not received from said specified acceptor devices on said NRFD line and DAC line, when using said second, high speed, data transmission protocol.

Claim 20

The combination of claim 13, said second sourcing means further including means for suspending transmission of further data bytes when any of said specified acceptor devices asserts a predefined suspend-transmission signal on one of said DAC and NRFD lines, and for resuming transmission of said further data bytes when said suspend-transmission signal on said one of said DAC and NRFD lines is deasserted.

Claim 21

The combination of claim 14, said source mode determination means further including means for deactivating said second sourcing means and activating said first sourcing means when any of said specified acceptor devices transmits a terminate-high-speed-mode message via said IEEE 488 bus.

Claim 24

The method of claim 16, said first bus interface, when using said second, high speed, data transmission protocol, further performing the steps of suspending transmission of further data bytes when any of said specified acceptor devices asserts a predefined suspend-transmission signal on one of said DAC and NRFD lines, and resuming transmission of said further data bytes when said suspend-transmission signal on said one of said DAC and NRFD lines is deasserted.

Claim 27

The method of claim 18, said first bus interface coordinating assertion of said data valid signal on said DAV line with interlock signals received from said specified acceptor devices on said NRFD line and DAC line when using said first, low speed, data transmission protocol, and said first bus interface asserting and deasserting said data valid signal on said DAV line in a predefined pulsing pattern, so long as (A) said sequence of data bytes are available for transmission, and (B) said interlock signals are not received from said specified acceptor devices on said NRFD line and DAC line, when using said second, high speed, data transmission protocol.

Claim 30

The method of claim 20, said second bus interface temporarily storing said received data bytes in a buffer prior to transmission thereof to said PG,54 one acceptor device, asserting a predefined suspend-transmission signal on one of said DAC and NRFD lines when said buffer has less than a predefined amount of unused storage capacity, and deasserting said suspend-transmission signal on said one of said DAC and NRFD lines when said buffer has at least said predefined amount of unused storage capacity.