Programmable logic device having a compressed configuration file and associated decompression

Claim 3

The method of claim 1, wherein said compressing step comprises: initializing a value of a count variable; counting a number of first logic level bits in said input file before detecting a second logic level bit; setting said value of said count variable equal to the result of said counting step; and generating a representation of said value of said count variable.

Claim 4

The method of claim 2 further comprising the steps of: counting said first logic level bits before detecting a second one of said second logic level bit; performing said setting and said generating steps; and re-initializing said value of said count variable.

Claim 5

The method of claim 3 further comprising generating said compressed configuration file from said representations of the value of said count variable.

Claim 6

The method of claim 4, wherein said compressed configuration file is generated by concatenating said representations.

Claim 7

The method of claim 2, wherein generating a representation of said count variable comprises generating a binary-coded hexadecimal equivalent of said value.

Claim 8

The method of claim 1, wherein said compressing step is done by an electronic compression circuit.

Claim 9

The method of claim 7, wherein said storage device comprises: said electronic compression circuit; electronically programmable read only memory for storing said compressed configuration file; and an electronic decompression circuit to perform said decompression step.

Claim 10

The method of claim 1, wherein said configuration file is larger than said compressed configuration file.

Claim 11

The method of claim 1, wherein said set of configuration data is equal in size to said configuration file.

Claim 12

The method of claim 1, wherein said decompression step is performed using a run-length decompression scheme.

Claim 15

The method of claim 12, wherein said compressing step comprises initializing a value of a count variable; counting a number of first logic level bits in said input file before detecting a second logic level bit setting said value of said count variable equal to the result of said counting step; and generating a representation of said value of said count variable.

Claim 16

The method of claim 13 further comprising the steps of: counting said first logic level bits before detecting a second one of said second logic level bit; performing said setting and said generating steps; and re-initializing said value of said count variable.

Claim 17

The method of claim 14 further comprising generating said compressed configuration file from said representations of the value of said count variable.

Claim 18

The method of claim 15, wherein said compressed configuration file is generated by concatenating said representations.

Claim 19

The method of claim 13, wherein generating a representation of said count variable comprises generating a binary-coded hexadecimal equivalent of said value.

Claim 20

The method of claim 12, wherein said compressing step is done by software in a digital computer.

Claim 21

The method of claim 12, wherein said compressing step is done by an electronic compression circuit.

Claim 22

The method of claim 12, wherein said configuration file is larger than said compressed configuration file.

Claim 23

The method of claim 12, wherein said set of configuration data is equal in size to said configuration file.

Claim 30

Apparatus as in claim 24, wherein said input file is larger than said first output file.

Claim 31

Apparatus as in claim 24, wherein said input file and said second output file are equal in size.

Claim 32

Apparatus as in claim 24, wherein said compression means comprises a software compression program running on a development computer.

Claim 33

Apparatus as in claim 24, wherein said compression means comprises a compression circuit associated with a development computer.

Claim 34

Apparatus as in claim 24, wherein said decompression means comprises a run-length decompression circuit.

Claim 35

Apparatus for run length compressing a serial data file having a plurality of first and second logic level bits wherein said apparatus requires only a single data clock, comprising: input terminal for inputting said serial data file; clock terminal for inputting said data clock; a counter having a plurality of inputs and outputs, said inputs connected so that said counter begins counting from zero when a reset signal is applied; a plurality of parallel-in registers with inputs coupled to outputs of said counter, and outputs generating a compressed data file; a logic gate with its inputs coupled to the outputs of said counter for generating a maximum signal indicating that said counter has reached its maximum count; and a first logic circuit for generating a grab signal with a first input coupled to said input terminal, a second input coupled to said clock terminal, a third input coupled to said maximum signal and a first output coupled to a clock input of said registers.

Claim 36

Apparatus for run length compressing a serial data file having a plurality of first and second logic level bits wherein said apparatus requires only a single data clock, comprising: input terminal for inputting said serial data file; clock terminal for inputting said data clock; a counter having a plurality of inputs and outputs, said inputs connected so that said counter begins counting from zero when a reset signal is applied; a plurality of parallel-in registers with inputs coupled to outputs of said counter, and outputs generating a compressed data file; a logic gate with its inputs coupled to the outputs of said counter for generating a maximum signal indicating that said counter has reached its maximum count; and a first logic circuit for generating a grab signal with a first input coupled to said input terminal, a second input coupled to said clock terminal, a third input coupled to said maximum signal and a first output coupled to a clock input of said registers.

Claim 37

The apparatus of claim 30, wherein said counter counts a number of said first logic level bits in said data file before one of said second logic level bits is detected by said logic circuit.

Claim 38

The apparatus of claim 30, wherein said plurality of registers comprise first and second registers and further comprising: a flip-flop with a clock input coupled to said grab signal, an first output coupled to a clock input of said first register and a second output coupled to a clock input of said second register.

Claim 39

The apparatus of claim 32, wherein said first register latches the output of said counter in response to said first clock signal.

Claim 40

The apparatus of claim 32, wherein said second register latches the output of said counter in response to said second output.