US5440718A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single semiconductor substrate RAM device utilizing data compressing/expanding mechanism in a multi-microprocessor environment
Assignee: Hitachi Ltd
•
Filing: 1994-09-19
•
Granted: 1995-08-08
•
Expires: 2014-09-19
Abstract
Abstract Compressor/expander circuits which are built in a common semiconductor substrate along with a random access memory unit function so as to realize compression/expansion processes merely through the internal data transfer controls between the circuits and the random access memory unit as based on built-in control unit. This endows the temporary storage of data and the compression/expansion processes hereof with continuities, and achieves higher speeds for the compression/expansion processes.
Inventors
- 👤 Takehiko Kumagai
- 👤 Takashi Kikuchi
- 👤 Takao Okubo
- 👤 Yasuyuki Fuse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 55
Claim 1
Independent Claim
351 words
A microcomputer system including: a first microprocessor coupled to a first bus means for communicating ordinary data and compressed data, the first microprocessor including a first memory means for storing the ordinary data and the compressed data, a first data transfer means for transferring the ordinary data and the compressed data between the first memory means and the first bus means, and a first central processor for controlling the first memory means and the first data transfer means; a second microprocessor coupled to a second bus means for communicating the ordinary data and the compressed data, the second microprocessor including a second memory means for storing ordinary data and the compressed data, a second data transfer means for transferring the ordinary data and the compressed data between the second memory means and the second bus means, and a second central processor for controlling the second memory means and the second data transfer means; and, a semiconductor memory device which is coupled to the first bus means and to the second bus means, said semiconductor memory device including: a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the ordinary data and the compressed data, and ii) an input and output means coupled to the memory array and said first bus means; a first circuit unit including a first serial input and output means coupled to the memory array, a second serial input and output means coupled to the memory array and the second bus means, a compression means, coupled to the first serial input and output means to the second serial input and output means, for generating the compressed data, and an expansion means, coupled to the first serial input and output means and to the second serial input and output means, for generating the ordinary data from the compressed data; and control means for controlling operations of the random access memory unit and the first circuit unit wherein both the compressed data and the ordinary data are stored in the random access memory unit after communication through the first circuit unit.
Claim 2
Dependent Claim
351 words
A microcomputer system including: a first microprocessor coupled to a first bus means for communicating ordinary data and compressed data, the first microprocessor including a first memory means for storing the ordinary data and the compressed data, a first data transfer means for transferring the ordinary data and the compressed data between the first memory means and the first bus means, and a first central processor for controlling the first memory means and the first data transfer means; a second microprocessor coupled to a second bus means for communicating the ordinary data and the compressed data, the second microprocessor including a second memory means for storing ordinary data and the compressed data, a second data transfer means for transferring the ordinary data and the compressed data between the second memory means and the second bus means, and a second central processor for controlling the second memory means and the second data transfer means; and, a semiconductor memory device which is coupled to the first bus means and to the second bus means, said semiconductor memory device including: a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the ordinary data and the compressed data, and ii) an input and output means coupled to the memory array and said first bus means; a first circuit unit including a first serial input and output means coupled to the memory array, a second serial input and output means coupled to the memory array and the second bus means, a compression means, coupled to the first serial input and output means to the second serial input and output means, for generating the compressed data, and an expansion means, coupled to the first serial input and output means and to the second serial input and output means, for generating the ordinary data from the compressed data; and control means for controlling operations of the random access memory unit and the first circuit unit wherein both the compressed data and the ordinary data are stored in the random access memory unit after communication through the first circuit unit.
Claim 3
Dependent Claim
37 words
The microcomputer system according to claim 1, wherein the first serial input and output means includes means for supplying the compression means with one of the compressed data and the ordinary data supplied from the memory army.
Claim 4
Dependent Claim
37 words
The microcomputer system according to claim 2, wherein the second serial input and output means includes means for selectively supplying the expansion means and the second bus means with the compressed data supplied from the memory array.
Claim 5
Dependent Claim
37 words
The microcomputer system according to claim 3, wherein the second serial input and output means includes means for selectively supplying the expansion means and the memory array with the compressed data supplied from the second bus means.
Claim 6
Dependent Claim
33 words
The microcomputer system according to claim 4, further comprising switching means for selectively coupling the first serial input and output means and the second serial input and output means with the memory array.
Claim 7
Dependent Claim
42 words
The microcomputer system according to claim 5, wherein the compression means includes means for first compressing the ordinary data supplied from the first serial input and output means and then supplying said second serial input and output means with the compressed data.
Claim 8
Dependent Claim
41 words
The microcomputer system according to claim 6, wherein the expansion means includes means for expanding the compressed data supplied from the second serial input and output means and then supplying the first serial input and output means with the ordinary data.
Claim 9
Dependent Claim
36 words
The microcomputer system according to claim 7, wherein the first serial input and output means includes means for selectively supplying the compression means and the memory array with the ordinary data supplied from the expansion means.
Claim 10
Dependent Claim
36 words
The microcomputer system according to claim 1, wherein an each of the plurality of memory cells of the memory array is a dynamic memory cell which includes an address selecting switch and an information storing capacitor.
Claim 11
Dependent Claim
288 words
A selective communication control device for communication of data including selectively expanded data and compressed data with a random access memory unit, the communication control device including a controller and a first circuit unit being formed on a single semiconductor substrate with the random access memory unit, wherein: the first circuit unit comprises: compressor circuit means for compressing the expanded data to form the compressed data; expander circuit means for expanding the compressed data to form the expanded data; a first external data terminal for communicating the expanded data with the control device; a second external data terminal for communicating the compressed data with the control device; first serial input and output circuit means for selectively communicating the expanded data to the compressor circuit means, to the random access memory unit, and to the first external data terminal; second serial input and output circuit means for selectively communicating the compressed data to the expander circuit means, to the random access memory unit, and to the second external data terminal; and, the controller comprises: means for selectively controlling a data communication path means through the first circuit unit for selective communication of the expanded data and the compressed data to the random access memory unit and to the first and second external data terminals, wherein the data communication path means comprises means for selectively communicating 1) the expanded data from the first external data terminal, through the first serial input and output circuit means to storage in the random access memory unit, and 2) the compressed data from the second external data terminal, through the second serial input and output circuit means and the expander circuit means to storage in the random access memory unit as the expanded data.
Claim 12
Dependent Claim
288 words
A selective communication control device for communication of data including selectively expanded data and compressed data with a random access memory unit, the communication control device including a controller and a first circuit unit being formed on a single semiconductor substrate with the random access memory unit, wherein: the first circuit unit comprises: compressor circuit means for compressing the expanded data to form the compressed data; expander circuit means for expanding the compressed data to form the expanded data; a first external data terminal for communicating the expanded data with the control device; a second external data terminal for communicating the compressed data with the control device; first serial input and output circuit means for selectively communicating the expanded data to the compressor circuit means, to the random access memory unit, and to the first external data terminal; second serial input and output circuit means for selectively communicating the compressed data to the expander circuit means, to the random access memory unit, and to the second external data terminal; and, the controller comprises: means for selectively controlling a data communication path means through the first circuit unit for selective communication of the expanded data and the compressed data to the random access memory unit and to the first and second external data terminals, wherein the data communication path means comprises means for selectively communicating 1) the expanded data from the first external data terminal, through the first serial input and output circuit means to storage in the random access memory unit, and 2) the compressed data from the second external data terminal, through the second serial input and output circuit means and the expander circuit means to storage in the random access memory unit as the expanded data.
Claim 13
Dependent Claim
42 words
The selective communication control device according to claim 10, wherein the first circuit unit further comprises selection circuit means for switching data communication paths relative to the first and second serial input and output circuit means and the random access memory unit.
Claim 14
Dependent Claim
280 words
A semiconductor memory device formed on a single semiconductor substrate including a random access memory unit and a first circuit unit, the semiconductor memory device comprising: a plurality of exterior terminals for communicating compressed data and ordinary data to the random access memory unit and to the first circuit unit; a first exterior terminal for communicating ordinary data to the random access memory unit and to the first input/output circuit unit; a second exterior terminal for communicating compressed data to the first circuit unit; control means for controlling operations of the random access memory unit and the first circuit unit in accordance with control signals wherein the compressed and ordinary data are stored in the random access memory unit after communication through the first circuit unit; a plurality of control signal terminals for communicating the control signals to the control means; the random access memory unit including: an input and output means coupled to the plurality of exterior terminals and to the first circuit unit for transmitting the ordinary data and the compressed data; and a memory array configured of a plurality of memory cells and coupled to the input and output means and to the first circuit unit, for storing the ordinary data and the compressed data; the first circuit unit including: a first input and output means, coupled to the memory array and to the first exterior terminal, for data communication; a second input and output means coupled to the memory array and to the second exterior terminal for data communication; compression means coupled to the first input and output means and to the second input and output means for expanding the compressed data into the ordinary data.
Claim 15
Dependent Claim
280 words
A semiconductor memory device formed on a single semiconductor substrate including a random access memory unit and a first circuit unit, the semiconductor memory device comprising: a plurality of exterior terminals for communicating compressed data and ordinary data to the random access memory unit and to the first circuit unit; a first exterior terminal for communicating ordinary data to the random access memory unit and to the first input/output circuit unit; a second exterior terminal for communicating compressed data to the first circuit unit; control means for controlling operations of the random access memory unit and the first circuit unit in accordance with control signals wherein the compressed and ordinary data are stored in the random access memory unit after communication through the first circuit unit; a plurality of control signal terminals for communicating the control signals to the control means; the random access memory unit including: an input and output means coupled to the plurality of exterior terminals and to the first circuit unit for transmitting the ordinary data and the compressed data; and a memory array configured of a plurality of memory cells and coupled to the input and output means and to the first circuit unit, for storing the ordinary data and the compressed data; the first circuit unit including: a first input and output means, coupled to the memory array and to the first exterior terminal, for data communication; a second input and output means coupled to the memory array and to the second exterior terminal for data communication; compression means coupled to the first input and output means and to the second input and output means for expanding the compressed data into the ordinary data.
Claim 16
Dependent Claim
285 words
A semiconductor memory device formed on a single semiconductor substrate and having a plurality of control signal terminals for communicating control signals into the device, and an external terminal for communicating expanded data to and from the device, the semiconductor memory device comprising: a plurality of data terminals for selectively communicating expanded data and compressed data to and from the device in response to predetermined ones of the control signals; a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the expanded data and the compressed data, and ii) a memory unit input and output means, coupling the memory array to ones of the plurality of data terminals, for communicating the expanded data and the compressed data to and from the random access memory unit; a first circuits including: a first input and output means, coupled to the memory array and to the external terminal, for supplying expanded data to and from the device, a second input and output means, coupled to the memory array, for supplying compressed data to and from the device, a compression means, coupled to the first input and output means and to the second input and output means, for generating the compressed data, and an expansion means, coupled to the first input and output means and to the second input and output means, for generating the expanded data; and control means, coupled to the control signal terminals, for controlling operations of the random access memory unit and the first circuit unit in accordance with the control signals wherein both the compressed data and the expanded data are stored in the random access memory unit after communication through the first circuit unit.
Claim 17
Dependent Claim
285 words
A semiconductor memory device formed on a single semiconductor substrate and having a plurality of control signal terminals for communicating control signals into the device, and an external terminal for communicating expanded data to and from the device, the semiconductor memory device comprising: a plurality of data terminals for selectively communicating expanded data and compressed data to and from the device in response to predetermined ones of the control signals; a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the expanded data and the compressed data, and ii) a memory unit input and output means, coupling the memory array to ones of the plurality of data terminals, for communicating the expanded data and the compressed data to and from the random access memory unit; a first circuits including: a first input and output means, coupled to the memory array and to the external terminal, for supplying expanded data to and from the device, a second input and output means, coupled to the memory array, for supplying compressed data to and from the device, a compression means, coupled to the first input and output means and to the second input and output means, for generating the compressed data, and an expansion means, coupled to the first input and output means and to the second input and output means, for generating the expanded data; and control means, coupled to the control signal terminals, for controlling operations of the random access memory unit and the first circuit unit in accordance with the control signals wherein both the compressed data and the expanded data are stored in the random access memory unit after communication through the first circuit unit.
Claim 18
Dependent Claim
36 words
The semiconductor memory device according to claim 13, wherein the first input and output means includes means for selectively supplying the compression means and the external terminal with the expanded data stored in the memory array.
Claim 19
Dependent Claim
31 words
The semiconductor memory device according to claim 14, wherein the second input and output means includes means for supplying the expansion means with the compressed data stored in the memory array.
Claim 20
Dependent Claim
36 words
The semiconductor memory device according to claim 15, wherein the first input and output means includes means for selectively supplying the compression means and the memory array with the expanded data communicated by the external terminal.
Claim 21
Dependent Claim
36 words
The semiconductor memory device according to claim 16, wherein the second input and output means includes means for selectively supplying the expansion means and the memory array with the compressed data generated by the compression means.
Claim 22
Dependent Claim
40 words
The semiconductor memory device according to claim 17, wherein the compression means includes means for compressing the expanded data supplied from the first input and output means and then supplying the second input and output means with the compressed data.
Claim 23
Dependent Claim
40 words
The semiconductor memory device according to claim 18, wherein the expansion means includes means for expanding the compressed data supplied from the second input and output means and then supplying the first input and output means with the expanded data.
Claim 24
Dependent Claim
27 words
The semiconductor memory device according to claim 19, further comprising switching means for selectively coupling the first and second input and output means with the memory array.
Claim 25
Dependent Claim
37 words
The semiconductor memory device according to claim 13, wherein an each of the plurality of memory cells of the memory array is a dynamic memory cell which includes an address selecting transistor and an information storing capacitor.
Claim 26
Dependent Claim
276 words
A semiconductor memory device formed on a single semiconductor substrate and having a plurality of control signal terminals for communicating control signals into the device and an external terminal for communicating comprised data to and from the device, the semiconductor memory device comprising: a plurality of exterior terminals for communicating expanded data and compressed data to and from the device; a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the compressed data and the expanded data, and ii) a memory unit input and output means coupling the memory array to the plurality of exterior terminals; a first circuit unit including a first input and output means coupled to thee memory array, a second input and output means coupling the memory array to the external terminal, a compression means, coupled to the first input and output means and to the second input and output means, for generating the compressed data, and an expansion means, coupled to the first input and output means and to the second input and output means, for generating the expanded data; and, control means coupled to the control signal terminals, for controlling operations of the random access memory unit and the first circuit unit in accordance with the control signals communicated into the device, wherein the compressed data is read into the semiconductor memory device through the external terminal, communicated through the second input and output means to the expansion means for expanding to the compressed data, and the expanded data is then communicated from the expansion means through the first input and output means and stored in the random access memory unit.
Claim 27
Dependent Claim
276 words
A semiconductor memory device formed on a single semiconductor substrate and having a plurality of control signal terminals for communicating control signals into the device and an external terminal for communicating comprised data to and from the device, the semiconductor memory device comprising: a plurality of exterior terminals for communicating expanded data and compressed data to and from the device; a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the compressed data and the expanded data, and ii) a memory unit input and output means coupling the memory array to the plurality of exterior terminals; a first circuit unit including a first input and output means coupled to thee memory array, a second input and output means coupling the memory array to the external terminal, a compression means, coupled to the first input and output means and to the second input and output means, for generating the compressed data, and an expansion means, coupled to the first input and output means and to the second input and output means, for generating the expanded data; and, control means coupled to the control signal terminals, for controlling operations of the random access memory unit and the first circuit unit in accordance with the control signals communicated into the device, wherein the compressed data is read into the semiconductor memory device through the external terminal, communicated through the second input and output means to the expansion means for expanding to the compressed data, and the expanded data is then communicated from the expansion means through the first input and output means and stored in the random access memory unit.
Claim 28
Dependent Claim
38 words
The semiconductor memory device according to claim 22, wherein the first input and output means includes means for supplying the compression means with a one of the expanded data and the compressed data stored in the memory array.
Claim 29
Dependent Claim
36 words
The semiconductor memory device according to claim 23, wherein the second input and output means includes means for selectively supplying the expansion means and the external terminal with the compressed data stored in the memory array.
Claim 30
Dependent Claim
36 words
The semiconductor memory device according to claim 24, wherein the first input and output means includes means for selectively supplying the compression means and the memory array with the expanded data generated by the expansion means.
Claim 31
Dependent Claim
40 words
The semiconductor memory device according to claim 25, wherein the second input and output means includes means for supplying the expansion means and the memory array with the compressed data read into the semiconductor memory device through the external terminal.
Claim 32
Dependent Claim
40 words
The semiconductor memory device according to claim 26, wherein the compression means includes means for compressing the expanded data supplied from the first input and output means and then supplying the second input and output means with the compressed data.
Claim 33
Dependent Claim
40 words
The semiconductor memory device according to claim 27, wherein the expansion means includes means for expanding the compressed data supplied from the second input and output means and then supplying the first input and output means with the expanded data.
Claim 34
Dependent Claim
32 words
The semiconductor memory device according to claim 28, further comprising switching means for selectively coupling the first input and output means and the second input and output means with the memory array.
Claim 35
Dependent Claim
38 words
The semiconductor memory device according to claim 22, wherein each of the plurality of memory cells of the random access memory unit is a dynamic memory cell which includes an address selecting transistor and an information storing capacitor.
Claim 36
Dependent Claim
256 words
A semiconductor memory device formed on a single semiconductor substrate and having a plurality of control signal terminals for communicating control signals into the device, a first external terminal for communicating ordinary data to and from the device, and a second external terminal for communicating compressed data to and from the device, the semiconductor memory device comprising: a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the ordinary data and the compressed data, and ii) a memory unit input and output means coupling the memory array to the first and second external terminals; a first circuit unit including a first input and output means coupling the memory array and the first external terminal, a second input and output means coupling the memory array and the second external terminal, a compression means, coupling the first input and output means to the second input and output means, for generating the compressed data, and an expansion means coupling the lust input and output means to the second input and output means, for generating the ordinary data from the compressed data; and, control means coupled to the control signal terminals, for controlling operations of the random access memory unit and the first circuit unit in accordance with the control signals communicated into the device, wherein the control means comprises means for supplying the ordinary data from the first external terminal through the first input and output means for storage directly into the random access memory unit as the ordinary data.
Claim 37
Dependent Claim
256 words
A semiconductor memory device formed on a single semiconductor substrate and having a plurality of control signal terminals for communicating control signals into the device, a first external terminal for communicating ordinary data to and from the device, and a second external terminal for communicating compressed data to and from the device, the semiconductor memory device comprising: a random access memory unit including i) a memory array configured of a plurality of memory cells for storing the ordinary data and the compressed data, and ii) a memory unit input and output means coupling the memory array to the first and second external terminals; a first circuit unit including a first input and output means coupling the memory array and the first external terminal, a second input and output means coupling the memory array and the second external terminal, a compression means, coupling the first input and output means to the second input and output means, for generating the compressed data, and an expansion means coupling the lust input and output means to the second input and output means, for generating the ordinary data from the compressed data; and, control means coupled to the control signal terminals, for controlling operations of the random access memory unit and the first circuit unit in accordance with the control signals communicated into the device, wherein the control means comprises means for supplying the ordinary data from the first external terminal through the first input and output means for storage directly into the random access memory unit as the ordinary data.
Claim 38
Dependent Claim
37 words
The semiconductor memory device according to claim 31, wherein the first input and output means includes means for selectively supplying the compression means and the first external terminal with the ordinary data supplied from the memory array.
Claim 39
Dependent Claim
37 words
The semiconductor memory device according to claim 32, wherein the second input and output means includes means for selectively supplying the expansion means and the second external terminal with the compressed data supplied from the memory array.
Claim 40
Dependent Claim
37 words
The semiconductor memory device according to claim 33, wherein the first input and output means includes means for selectively supplying the compression means and the memory array with the ordinary data supplied from the first external terminal.
Claim 41
Dependent Claim
37 words
The semiconductor memory device according to claim 34, wherein the second input and output means includes means for selectively supplying the expansion means and the memory array with the compressed data supplied from the second external terminal.
Claim 42
Dependent Claim
40 words
The semiconductor memory device according to claim 35, wherein the compression means includes means for compressing the ordinary data supplied from the first input and output means and then supplying the second input and output means with the compressed data.
Claim 43
Dependent Claim
40 words
The semiconductor memory device according to claim 36, wherein the expansion means includes means for expanding the compressed data supplied from the second input and output means and then supplying the first input and output means with the ordinary data.
Claim 44
Dependent Claim
32 words
The semiconductor memory device according to claim 37, further comprising switching means for selectively coupling the first input and output means and the second input and output means with the memory array.
Claim 45
Dependent Claim
33 words
The semiconductor memory device according to claim 31, wherein an each of the plurality of memory cells is a dynamic memory cell which includes an address selecting transistor and an information storing capacitor.
Claim 46
Dependent Claim
247 words
A microcomputer system including: a first microprocessor including a first semiconductor memory device coupled to a bus means, and a first central processor for controlling the first semiconductor memory device; and, a second microprocessor including a second semiconductor memory device coupled to the bus means, and a second central processor for controlling the second semiconductor memory device; the first and second semiconductor memory devices being included respectively in the first and second microprocessors, each of the first and second semiconductor memory devices including: a memory array formed of a plurality of memory cells for storing data including expanded data compressed data; a first circuit unit having a first input and output means coupled to the memory array and to the bus means, a second input and output means coupled to the memory array and the bus means, a compression means, coupled to the first input and output means and to the second input and output means, for generating the compressed data, and an expansion means, coupled to the first input and output means and to the second input and output means, for generating the expanded data; and control means coupled to the first central processor and to the second central processor, for controlling operation of the first circuit unit in accordance with control signals supplied from the first central processor and the second central processor wherein both the compressed data and the expanded data is stored in the memory array after communication through the first circuit unit.
Claim 47
Dependent Claim
247 words
A microcomputer system including: a first microprocessor including a first semiconductor memory device coupled to a bus means, and a first central processor for controlling the first semiconductor memory device; and, a second microprocessor including a second semiconductor memory device coupled to the bus means, and a second central processor for controlling the second semiconductor memory device; the first and second semiconductor memory devices being included respectively in the first and second microprocessors, each of the first and second semiconductor memory devices including: a memory array formed of a plurality of memory cells for storing data including expanded data compressed data; a first circuit unit having a first input and output means coupled to the memory array and to the bus means, a second input and output means coupled to the memory array and the bus means, a compression means, coupled to the first input and output means and to the second input and output means, for generating the compressed data, and an expansion means, coupled to the first input and output means and to the second input and output means, for generating the expanded data; and control means coupled to the first central processor and to the second central processor, for controlling operation of the first circuit unit in accordance with control signals supplied from the first central processor and the second central processor wherein both the compressed data and the expanded data is stored in the memory array after communication through the first circuit unit.
Claim 48
Dependent Claim
41 words
The microcomputer system according to claim 40, wherein the first input and output means includes means for selectively supplying the compression means and the bus means with a one of the compressed data and expanded data supplied from the memory array.
Claim 49
Dependent Claim
35 words
The microcomputer system according to claim 40, wherein the second input and output means includes means for selectively supplying the expansion means and the bus means with the compressed data supplied from the memory array.
Claim 50
Dependent Claim
35 words
The microcomputer system according to claim 42, wherein the first input and output means includes means for selectively supplying the compression means and the memory array with the expanded data supplied from the bus means.
Claim 51
Dependent Claim
35 words
The microcomputer system according to claim 43, wherein the second input and output means includes means for selectively supplying the expansion means and the memory array with the compressed data supplied from the bus means.
Claim 52
Dependent Claim
39 words
The microcomputer system according to claim 44, wherein the compression means includes means for compressing the expanded data supplied from the first input and output means and then supplying the second input and output means with the compressed data.
Claim 53
Dependent Claim
44 words
The microcomputer system according to claim 45, wherein the expansion means includes means for expanding the compressed data supplied from the second input and output means as first expanded data and then supplying the first input and output means with the first expanded data.
Claim 54
Dependent Claim
30 words
The microcomputer system according to claim 46, further comprising switching means for selectively coupling the first input and output means and the second input and output means with memory array.
Claim 55
Dependent Claim
36 words
The microcomputer system according to claim 40, wherein an each of the plurality of memory cells of the memory array is a dynamic memory cell which includes and address selecting MOSFET and an information storing capacitor.
References Cited (Backward Citations)
US4386416A
Cited
US4454575A
Cited
US4491909A
Cited
US5129061A
Cited
US4626824A
Cited
US4730348A
Cited
US4918588A
Cited
JPS63183699A
Cited
JPS63204594A
Cited
US5210851A
Cited
US4937681A
Cited
US5057932A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |