Patent US5563528A successfully refreshed from Google Patents.
US5563528A
Expired / Lapsed
US
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Multiplexer for programmable logic device
Assignee: Xilinx Inc
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Filing: 1995-05-02
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Granted: 1996-10-08
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Expires: 2015-05-02
Abstract
Abstract A multiplexer for a programmable logic device (PLD) includes a control line decode circuit that substantially reduces the number of control lines necessary to program a multiplexer. Each multiplexer input line is programmably connected to at least three output lines to increase the number of routing options. A TTL buffer circuit located at the output of the multiplexer provides the user with various output signal options, whereas a word line driver coupled to the TTL buffer circuit increases signal drive. Local feedback signals are provided to the multiplexer to increase PLD functionality. Signals from the I/O pads are routed directly to the multiplexer rather than the UIM, thereby improving PLD speed. Moreover, using the multiplexer minimizes the number of input lines because the UIM is still available for routing connections. Therefore, the present invention provides both fast cycle time and fast multiple level logic.
Inventors
- 👤 Sholeh Diba
- 👤 Joshua M. Silver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1733; H03K19/1737; H03K19/17704
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
67 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines having multiple signal sources from different devices on said programmable logic device and a plurality of multiplexer output lines.
Claim 2
Dependent Claim
67 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines having multiple signal sources from different devices on said programmable logic device and a plurality of multiplexer output lines.
Claim 3
Dependent Claim
27 words
The multiplexer of claim 1 further comprising: a word line driver in communication with said multiplexer output lines for amplifying output signals present on said output lines.
Claim 4
Dependent Claim
51 words
The multiplexer of claim 2 further including a buffer circuit which comprises: means for providing complementary outputs for each multiplexer output signal that is provided as an input to said word line driver; and means for selecting a predetermined edge of a signal to be provided to said word line driver.
Claim 5
Dependent Claim
22 words
The multiplexer of claim 1 further comprising: a plurality of input pins in direct communication with said plurality of multiplexer input lines.
Claim 6
Dependent Claim
82 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines; and means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing a power-up or a ground control signal through said multiplexer.
Claim 7
Dependent Claim
82 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines; and means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing a power-up or a ground control signal through said multiplexer.
Claim 8
Dependent Claim
81 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines; and means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing a plurality of localized feedback signals through said multiplexer.
Claim 9
Dependent Claim
81 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines; and means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing a plurality of localized feedback signals through said multiplexer.
Claim 10
Dependent Claim
94 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines: and means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing a plurality of signals through said multiplexer, each multiplexer input line interconnecting to any one of at least three multiplexer output lines.
Claim 11
Dependent Claim
94 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines: and means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing a plurality of signals through said multiplexer, each multiplexer input line interconnecting to any one of at least three multiplexer output lines.
Claim 12
Dependent Claim
80 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines, wherein each multiplexer input line is assigned for interconnection to any one of at least three multiplexer output lines in accordance with a predetermined pattern.
Claim 13
Dependent Claim
80 words
A multiplexer for a programmable logic device comprising: a decode circuit for receiving N control signals, wherein N is a number greater than 1, and decoding said control signals to generate 2 N program signals that program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines, wherein each multiplexer input line is assigned for interconnection to any one of at least three multiplexer output lines in accordance with a predetermined pattern.
Claim 14
Dependent Claim
62 words
A multiplexer for a programmable logic device comprising: means for establishing interconnections between a plurality of multiplexer input lines having multiple signal sources from different devices on said programmable logic device and a plurality of multiplexer output lines to route a plurality of signals through said multiplexer, each multiplexer input line interconnecting to any one of at least three multiplexer output lines.
Claim 15
Dependent Claim
62 words
A multiplexer for a programmable logic device comprising: means for establishing interconnections between a plurality of multiplexer input lines having multiple signal sources from different devices on said programmable logic device and a plurality of multiplexer output lines to route a plurality of signals through said multiplexer, each multiplexer input line interconnecting to any one of at least three multiplexer output lines.
Claim 16
Dependent Claim
69 words
A multiplexer for a programmable logic device comprising; means for establishing interconnections between a plurality of multiplexer input lines and a plurality of multiplexer output lines to route a plurality of signals through said multiplexer, each multiplexer input line interconnecting to at least three multiplexer output lines, wherein said multiplexer input lines are assigned for interconnection to said at least three multiplexer lines in accordance with a predetermined pattern.
Claim 17
Dependent Claim
69 words
A multiplexer for a programmable logic device comprising; means for establishing interconnections between a plurality of multiplexer input lines and a plurality of multiplexer output lines to route a plurality of signals through said multiplexer, each multiplexer input line interconnecting to at least three multiplexer output lines, wherein said multiplexer input lines are assigned for interconnection to said at least three multiplexer lines in accordance with a predetermined pattern.
Claim 18
Dependent Claim
62 words
The multiplexer of claim 10 further comprising: a decode circuit for receiving N control signals wherein N is a number greater than 1, and to decode said N control signals to produce 2 N control signals that are routed to said multiplexer to program interconnections within said multiplexer between a plurality of multiplexer input lines and a plurality of multiplexer output lines.
Claim 19
Dependent Claim
72 words
The multiplexer of claim 10 wherein said programmable logic device further comprises: a word line driver in communication with said multiplexer output lines for amplifying output signals present on said multiplexer output lines; means for providing complementary output signals for each multiplexer output signal that is provided as an input signal to said word line driver; and means for selecting a predetermined edge of a signal provided to said word line driver.
Claim 20
Dependent Claim
22 words
The multiplexer of claim 10 further comprising: said plurality of input pins in direct communication with a plurality of multiplexer input lines.
Claim 21
Dependent Claim
34 words
The multiplexer of claim 10 further comprising: means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing any of power up and ground control signals through said multiplexer.
Claim 22
Dependent Claim
32 words
The multiplexer of claim 10 further comprising: means for establishing interconnections between said multiplexer input lines and said multiplexer output lines for routing a plurality of localized feedback signals through said multiplexer.
Claim 23
Dependent Claim
34 words
A multiplexer of claim 10 wherein said programmable logic device further comprises: a word line driver in direct communication with said multiplexer output lines for amplifying output signals present on said multiplexer output lines.
Claim 24
Dependent Claim
29 words
The multiplexer of claim 16 further comprising: means for providing complementary output signals for each multiplexer output signal that is provided as an input to said word line driver.
Claim 25
Dependent Claim
17 words
The multiplexer of claim 16 further comprising: means for selecting a word line driver output signal characteristic.
Claim 26
Dependent Claim
22 words
The multiplexer of claim 16 further comprising: a plurality of input pins in direct communication with a plurality of multiplexer input lines.
Claim 27
Dependent Claim
35 words
The multiplexer of claim 16 further comprising: means for establishing interconnections between a plurality of multiplexer input lines and said multiplexer output lines for routing any power up and ground control signals through said multiplexer.
Claim 28
Dependent Claim
34 words
The multiplexer of claim 16 further comprising: means for establishing interconnections between a plurality of multiplexer input lines and said multiplexer output lines for routing a plurality of localized feedback signals through said multiplexer.
Claim 29
Dependent Claim
53 words
A programmable logic device comprising: a plurality of input pads; a universal interconnect matrix; a multiplexer for receiving signals directly from said plurality of input pads and said universal interconnect matrix; a buffer circuit for receiving signals from said multiplexer; and a plurality of output pads for receiving signals from said buffer circuit.
Claim 30
Dependent Claim
53 words
A programmable logic device comprising: a plurality of input pads; a universal interconnect matrix; a multiplexer for receiving signals directly from said plurality of input pads and said universal interconnect matrix; a buffer circuit for receiving signals from said multiplexer; and a plurality of output pads for receiving signals from said buffer circuit.
References Cited (Backward Citations)
US4048626A
Cited
US4721868A
Cited
US5130704A
Cited
US4871930A
Cited
US5268598A
Cited
US5311479A
Cited
US5446700A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |