Decoder circuit having CMOS inverter circuits

Claim 1

A semiconductor device comprising: a plurality of memory cell blocks arranged in pairs, each memory cell block including a plurality of memory cell transistors constituting a NOR-type mask ROM having gates which are coupled to word lines, each memory cell block further including a block selecting enhancement type MOS transistor and a block selecting depletion type MOS transistor connected in series with said memory cell transistors, wherein a gate of the block selecting enhancement type MOS transistor in one memory cell block of a given pair and a gate of the block selecting depletion type MOS transistor in the other memory cell block of said given pair are commonly connected to one of a plurality of block selection lines; and a decoder circuit for selecting one of said memory cells of one of said memory cell blocks by driving said block selection lines and said word lines, said decoder circuit comprising: a main decoder portion for outputting a main decoder portion output signal; block selection line drive logic having a plurality of input nodes applied with said main decoder portion output signal and block selection signals, for driving one of said block selection lines in accordance with said main decoder portion output signal and said block selection signals; and a plurality of CMOS inverters, each CMOS inverter comprising a P channel MOS transistor and an N channel MOS transistor, a source of said P channel MOS transistor applied with said main decoder portion output signal, a source of said N channel MOS transistor applied with a predetermined potential, gates of said P channel MOS transistor and said N channel MOS transistor connected to a corresponding one of a plurality of word line selection signal lines, and drains of said P channel MOS transistor and said N channel MOS transistor connected to a corresponding one of said word lines.