← Back to Patent Explorer
US5563079A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a field effect transistor

Assignee: LG Electronics Inc
•
Filing: 1993-06-09
•
Granted: 1996-10-08
•
Expires: 2013-06-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of making a FET includes the steps of forming a source and a drain at respective edges of the surface of a semiconductor substrate, forming a first insulation film on the whole surfaces of the semiconductor substrate, the source, and the drain, coating a photoresist on the first insulation film, patterning the photoresist using a photolithography process to form a photoresist pattern having a first space corresponding to a gate length between the source and the drain, forming a second insulating film on the whole surfaces of the exposed first insulation film and the photoresist pattern, etching the second insulation film to form sidewall insulation films at the sidewalls of the photoresist patterns, etching the first insulation film using the sidewall insulation films and the photoresist pattern as an etching mask to form first insulation film patterns, which form a second space having a width smaller than that of the first space, beneath the first space, removing the sidewall insulation films to form a T-shaped space, and depositing a conductor to form a T-shaped gate in the T-shaped space.

Inventors

  • 👤 Jin H. Shin
  • 👤 Young S. Kwon
  • 👤 Chang T. Kim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 19:13
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10P; H10P76/00; H10P76/20; H10P76/202; H10P76/40; H10P76/408; H10P76/4088

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 276 words
A method of making an FET having a semiconductor substrate, a source, and a drain, the method comprising the steps of: (a) forming the source and the drain at respective locations on a surface of the semiconductor substrate; (b) forming a first insulation film on said surface of the semiconductor substrate and the source and the drain; (c) coating a photoresist on the first insulation film; (d) patterning the photoresist using a photolithography process to form a photoresist pattern, an edge portion of said photoresist pattern having sidewalls defining a first space, said first space exposing a portion of said first insulation film corresponding to a gate length between the source and the drain; (e) forming a second insulating film on said exposed portion of the first insulation film and the patterned photoresist including said sidewalls of said patterned photoresist; (f) etching the second insulation film to form sidewall insulation films at said sidewalls of the patterned photoresist defining the first space; (g) etching the first insulation film using the sidewall insulation films and the photoresist pattern as an etching mask to form first insulation film patterns, said first insulation film patterns forming a second space beneath the first space, the second space having a width smaller than a width of the first space; (h) removing the sidewall insulation films to form a T-shaped space; (i) depositing a conductive material to form a T-shaped gate in the T-shaped space, said conductive material also being deposited on said patterned photoresist; (j) removing the patterned photoresist and said conductive material deposited on the patterned photoresist after forming the T-shaped gate; and (k) removing the first insulation film patterns.
Claim 2
Independent Claim 276 words
A method of making an FET having a semiconductor substrate, a source, and a drain, the method comprising the steps of: (a) forming the source and the drain at respective locations on a surface of the semiconductor substrate; (b) forming a first insulation film on said surface of the semiconductor substrate and the source and the drain; (c) coating a photoresist on the first insulation film; (d) patterning the photoresist using a photolithography process to form a photoresist pattern, an edge portion of said photoresist pattern having sidewalls defining a first space, said first space exposing a portion of said first insulation film corresponding to a gate length between the source and the drain; (e) forming a second insulating film on said exposed portion of the first insulation film and the patterned photoresist including said sidewalls of said patterned photoresist; (f) etching the second insulation film to form sidewall insulation films at said sidewalls of the patterned photoresist defining the first space; (g) etching the first insulation film using the sidewall insulation films and the photoresist pattern as an etching mask to form first insulation film patterns, said first insulation film patterns forming a second space beneath the first space, the second space having a width smaller than a width of the first space; (h) removing the sidewall insulation films to form a T-shaped space; (i) depositing a conductive material to form a T-shaped gate in the T-shaped space, said conductive material also being deposited on said patterned photoresist; (j) removing the patterned photoresist and said conductive material deposited on the patterned photoresist after forming the T-shaped gate; and (k) removing the first insulation film patterns.
Claim 3
Dependent Claim 38 words
A method in accordance with claim 1, further comprising the step of: (l) forming a third insulation film serving as a protection film on an exposed portion of the substrate, the source, the drain and the T-shaped gate.
Claim 4
Dependent Claim 19 words
A method in accordance with claim 1, wherein the removing step (j) is carried out using a lift-off process.
Claim 5
Dependent Claim 29 words
A method in accordance with claim 1, further comprising a step of performing a heat-treatment process to harden the first insulation film between the step(b) and the step (c).
Claim 6
Dependent Claim 26 words
A method in accordance with claim 1, wherein the first insulation film is formed with an etch selectivity higher than that of the second insulation film.
Claim 7
Dependent Claim 22 words
A method in accordance with claim 1, wherein the first insulation film is made of one of a photoresist and a polyimide.
Claim 8
Dependent Claim 19 words
A method in accordance with claim 1, wherein the etching step (f) is carried out by an RIE method.
Claim 9
Dependent Claim 18 words
A method in accordance with claim 7, wherein the RIE method uses CF 4 as an etch gas.
Claim 10
Dependent Claim 24 words
A method in accordance with claim 1, wherein the second insulation film is formed using one of a sputtering method and a PECVD method.
Claim 11
Dependent Claim 18 words
A method in accordance with claim 1, wherein the sidewall insulation films are removed by an HF solution.
Claim 12
Dependent Claim 18 words
A method in accordance with claim 1, wherein the second insulation film is made of SiO 2 .
Claim 13
Dependent Claim 24 words
A method in accordance with claim 1, wherein the gate is made of one of a metal and a polysilicon having a conductivity type.

References Cited (Backward Citations)

JPS57183037A Cited
JPS60234375A Cited
JPS63131523A Cited
US4910157A Cited
US4997778A Cited
US4929567A Cited
US4959326A Cited
JPH0323643A Cited
JPH03165526A Cited
US4996167A Cited
US5182218A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-10-08 2000-04-08 2000-10-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-10-08 2004-04-08 2004-10-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-10-08 2008-04-08 2008-10-08 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag