US5182218A
Expired / Lapsed
US
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Production methods for compound semiconductor device having lightly doped drain structure
Assignee: Sumitomo Electric Industries Ltd
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Filing: 1992-02-20
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Granted: 1993-01-26
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Expires: 2012-02-20
Abstract
Abstract The present invention relates to a method of making a compound semiconductor device having a high performance self-aligned LDD structure which has stable characteristics, and is suitable for high integration and high yield, in which after forming a channel layer beneath the substrate surface, using a high performed self-aligned technology, a gate electrode, lightly doped layers and heavily doped layers are formed in predetermined positions by a photolithography for the gate portion. This process of a photolithography is performed only once, therefore, each pattern can be formed with excellent accuracy and reproducibility.
Inventors
- 👤 Mitsuaki Fujihira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; Y; Y10; Y10S; Y10S148/00; Y10S148/10
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
273 words
A method of making a compound semiconductor device having a field effect transistor structure, comprising: a first step of forming a channel layer on a surface of a semiconductor substrate by forming a surface protection layer on said substrate, forming a first resist pattern having an opening in a position corresponding to a element forming area on said surface protection layer, and performing an ion implantation with using a first resist pattern as a mask; the second step of forming an second resist pattern having a having an opening in a only position corresponding to a gate electrode forming area and thereafter removing said surface protection layer in only a position in which said surface protection layer is exposed through said opening of said second resist pattern; the third step of depositing gate electrode material on the whole surface of the substrate to form a gate portion on said channel layer; the forth step of etching said second resist pattern with using said gate electrode material as a mask to remove said second resist pattern in a vicinity of said gate portion; the fifth step of depositing insulation material on whole of the substrate to form a gate pattern covering said gate portion and thereafter removing said second resist pattern; a sixth step of performing ion implantation to said substrate using said first resist pattern and said gate pattern as masks, to form heavily doped layer; and a seventh step of removing said gate pattern by etching, and thereafter performing ion implantation to said substrate using said gate portion and said first resist pattern as a mask to form a lightly doped layer.
Claim 2
Independent Claim
273 words
A method of making a compound semiconductor device having a field effect transistor structure, comprising: a first step of forming a channel layer on a surface of a semiconductor substrate by forming a surface protection layer on said substrate, forming a first resist pattern having an opening in a position corresponding to a element forming area on said surface protection layer, and performing an ion implantation with using a first resist pattern as a mask; the second step of forming an second resist pattern having a having an opening in a only position corresponding to a gate electrode forming area and thereafter removing said surface protection layer in only a position in which said surface protection layer is exposed through said opening of said second resist pattern; the third step of depositing gate electrode material on the whole surface of the substrate to form a gate portion on said channel layer; the forth step of etching said second resist pattern with using said gate electrode material as a mask to remove said second resist pattern in a vicinity of said gate portion; the fifth step of depositing insulation material on whole of the substrate to form a gate pattern covering said gate portion and thereafter removing said second resist pattern; a sixth step of performing ion implantation to said substrate using said first resist pattern and said gate pattern as masks, to form heavily doped layer; and a seventh step of removing said gate pattern by etching, and thereafter performing ion implantation to said substrate using said gate portion and said first resist pattern as a mask to form a lightly doped layer.
Claim 3
Dependent Claim
21 words
A method according to claim 1, wherein the etching of said forth step is performed by a reactive ion etching method.
Claim 4
Dependent Claim
23 words
A method according to claim 1, wherein the formation of said gate pattern in said fifth step is performed by a sputtering method.
Claim 5
Dependent Claim
35 words
A method according to claim 1, wherein said gate pattern is made of a material having a higher etching rate than that of said surface protection layer in an etching process of said seventh step.
Claim 6
Dependent Claim
25 words
A method according to claim 1, wherein said surface protection layer is made of Silicon Oxide, and said gate pattern is made of Silicon Nitride.
Claim 7
Dependent Claim
18 words
A method according to claim 1, wherein said gate electrode material comprises metal having a high melting point.
Claim 8
Dependent Claim
19 words
A method according to claim 1, wherein said gate electrode material comprises metal silicide having a high melting point.
Claim 9
Independent Claim
242 words
A method of making a compound semiconductor device having a field effect transistor structure comprising: a first step of forming a channel layer in a semiconductor substrate with using a first resist pattern having an opening in a position corresponding an element forming area, thereafter depositing gate electrode material on the substrate, and forming a second resist pattern having an opening in a position corresponding to a gate electrode forming area on said gate electrode material deposited on the substrate; a second step of depositing a first insulating material to form a first gate pattern on said gate electrode forming area, and removing said second resist pattern in an area over said gate electrode forming area by etching; a third step of depositing a insulating material on the substrate to form a second gate pattern covering said first gate pattern, and thereafter removing all of said resist pattern; a fourth step of selectively removing said gate electrode material with using said second gate pattern as a mask, and performing ion implantation on the substrate to form heavily doped layer; a fifth step of removing said second gate pattern and removing said gate electrode material exposed by removing said second gate pattern with using said first gate pattern as a mask to form a gate portion; and a sixth step of performing ion implantation with using said gate portion and said first gate pattern as a mask to form a lightly doped layer.
Claim 10
Independent Claim
242 words
A method of making a compound semiconductor device having a field effect transistor structure comprising: a first step of forming a channel layer in a semiconductor substrate with using a first resist pattern having an opening in a position corresponding an element forming area, thereafter depositing gate electrode material on the substrate, and forming a second resist pattern having an opening in a position corresponding to a gate electrode forming area on said gate electrode material deposited on the substrate; a second step of depositing a first insulating material to form a first gate pattern on said gate electrode forming area, and removing said second resist pattern in an area over said gate electrode forming area by etching; a third step of depositing a insulating material on the substrate to form a second gate pattern covering said first gate pattern, and thereafter removing all of said resist pattern; a fourth step of selectively removing said gate electrode material with using said second gate pattern as a mask, and performing ion implantation on the substrate to form heavily doped layer; a fifth step of removing said second gate pattern and removing said gate electrode material exposed by removing said second gate pattern with using said first gate pattern as a mask to form a gate portion; and a sixth step of performing ion implantation with using said gate portion and said first gate pattern as a mask to form a lightly doped layer.
Claim 11
Dependent Claim
21 words
A method according to claim 8, wherein the etching of said second step is performed by a reactive ion etching method.
Claim 12
Dependent Claim
28 words
A method according to claim 8, wherein the formation of said first and second gate patterns in said second and third steps are performed by a sputtering method.
Claim 13
Dependent Claim
36 words
A method according to claim 8, wherein said second gate pattern is made of a material having a higher etching rate than that of said second gate pattern in an etching process of said fifth step.
Claim 14
Dependent Claim
26 words
A method according to claim 8, wherein said first gate pattern is made of Silicon Oxide, and said second gate pattern is made of tungsten silicide.
Claim 15
Dependent Claim
18 words
A method according to claim 8, wherein said gate electrode material comprises metal having a high melting point.
Claim 16
Dependent Claim
19 words
A method according to claim 8, wherein said gate electrode material comprises metal silicide having a high melting point.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-26 | 1996-07-27 | 1997-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-26 | 2000-07-27 | 2001-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-26 | 2004-07-27 | 2005-01-26 | $7700.00 | Window Closed / Lapsed |