US5559840A — Digital timing recovery method and apparatus for …

Claim 1

Independent Claim 194 words

In a signal processing channel for recovering coded binary data from an analog signal having extrema, said channel having clock means for generating a channel clock signal and sampling means for sampling said analog signal to produce a plurality of sequential signal samples {S i } responsive to said channel clock signal, wherein i is an integer, a method for phase-synchronizing said channel clock signal to said analog signal, said method comprising the steps of: (a) producing a multiplicity of digital signals {y i } representing said sequential signal samples {S i }; b) encoding a predetermined number of said digital signals {y i } to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; (c) producing a digital clock phase error signal (PES) e i in response to each sequence of three adjacent said detector codes (d i-1 , d i , d i+1 ); and (d) adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 2

Dependent Claim 194 words

In a signal processing channel for recovering coded binary data from an analog signal having extrema, said channel having clock means for generating a channel clock signal and sampling means for sampling said analog signal to produce a plurality of sequential signal samples {S i } responsive to said channel clock signal, wherein i is an integer, a method for phase-synchronizing said channel clock signal to said analog signal, said method comprising the steps of: (a) producing a multiplicity of digital signals {y i } representing said sequential signal samples {S i }; b) encoding a predetermined number of said digital signals {y i } to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; (c) producing a digital clock phase error signal (PES) e i in response to each sequence of three adjacent said detector codes (d i-1 , d i , d i+1 ); and (d) adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 3

Dependent Claim 136 words

The method of claim 1 wherein said encoding step (b) comprises the steps of: (b.1) acquiring the preceding said digital signal y i-1 and the succeeding said digital signal y i+1 for said each digital signal y i ; (b.2) if (y i >y i-1 ) and (y i ≦y i+1 ) and (y i >k + ) or (y i <y i-1 ) and (y i ≦y i+1 ) and (y i <k - ), wherein k + and k - are predetermined threshold values, selecting said digital detector code d i =1 to indicate the occurrence of an analog signal extremum near said signal sample S i ; otherwise (b.3) selecting said digital detector code d i =0 to indicate no occurrence of an analog signal extremum near said signal sample S i .

Claim 4

Dependent Claim 42 words

The method of claim 2 wherein said producing step (c) comprises the step of: (c.1) producing a digital clock PES e i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Claim 5

Dependent Claim 98 words

The method of claim 3 wherein said producing step (c) further comprises the steps of: (c.2) setting a flag signal F i =1 and storing a hold signal H i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(0,0,1); and (c.3) producing a digital clock PES e i =F i-1 (H i-1 -y i *sign(y i-1 )) and resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0).

Claim 6

Dependent Claim 98 words

The method of claim 3 wherein said producing step (c) further comprises the steps of: (c.2) setting a flag signal F i =1 and storing a hold signal H i =y i *sign(y i-1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0); and (c.3) producing a digital clock PES e i =F i-1 (y i *sign(y i+1 )-H i-1 ) and resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d 1+1 )=(0,0,1).

Claim 7

Dependent Claim 102 words

The method of claim 3 wherein said producing step (c) further comprises the steps of: (c.2) setting a flag signal F i =1 responsive to a digital code sequence (d i-1 , d i , d i+1 )=(0,0,1); (c.3) producing a digital clock PES e i =F i-1 (y i-2 -y i )*sign(y i-1 ) and resetting said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0); and (c.4) resetting said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Claim 8

Dependent Claim 249 words

In a signal processing channel for recovering coded binary data from an analog signal having extrema, said channel having clock means for generating a channel clock signal and sampling means for sampling said analog signal to produce a plurality of sequential signal samples {S i } responsive to said channel clock signal, wherein i is an integer, a clock phase error correction circuit comprising: converter means coupled to said sampling means and to said clock means for producing a multiplicity of digital signals {y i } representing said sequential samples {S i }; register means coupled to said converter means for storing a sequence of at least three sequential said digital signals (y i-1 , y i , y i-1 ); peak detector means coupled to said register means for encoding each said sequence of digital signals to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; error means coupled to said peak detector means for producing a digital clock phase error signal (PES) e i in response to each sequence of at least three adjacent said detector codes (d i-1 , d i , d i+1 ); and phase adjusting means coupled to said error means and to said clock means for adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 9

Dependent Claim 249 words

In a signal processing channel for recovering coded binary data from an analog signal having extrema, said channel having clock means for generating a channel clock signal and sampling means for sampling said analog signal to produce a plurality of sequential signal samples {S i } responsive to said channel clock signal, wherein i is an integer, a clock phase error correction circuit comprising: converter means coupled to said sampling means and to said clock means for producing a multiplicity of digital signals {y i } representing said sequential samples {S i }; register means coupled to said converter means for storing a sequence of at least three sequential said digital signals (y i-1 , y i , y i-1 ); peak detector means coupled to said register means for encoding each said sequence of digital signals to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; error means coupled to said peak detector means for producing a digital clock phase error signal (PES) e i in response to each sequence of at least three adjacent said detector codes (d i-1 , d i , d i+1 ); and phase adjusting means coupled to said error means and to said clock means for adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 10

Dependent Claim 137 words

The clock phase error correction circuit of claim 7 wherein said peak detector means further comprises: peak logic means for comparing said three sequential digital signals (y i-1 , y i , y i+1 ) and for selecting said digital detector code d i such that, if (y i >y i-1 ) and (y i ≧y i+1 ) and (y i >k + ) or (y i <y i-1 ) and (y i <y i+1 ) and (y i <k - ), wherein k + and k - are predetermined threshold values, said digital detector code d i =1 indicating the occurrence of an analog signal extremum near said signal sample S i , otherwise said digital detector code d i =0 indicating no occurrence of an analog signal extremum near said signal sample S i .

Claim 11

Dependent Claim 48 words

The clock phase error correction circuit of claim 8 wherein said peak logic means further comprises: first PES logic means for producing a digital clock PES e i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Claim 12

Dependent Claim 148 words

The clock phase error correction circuit of claim 9 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; hold register means for storing a hold signal H i ; second PES logic means coupled to said flag means and to said hold register means for setting said flag signal F i =1 and for setting said hold signal H i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(0,0,1); and third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (H i-1 -y i *sign(y i-1 )) and for resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0).

Claim 13

Dependent Claim 148 words

The clock phase error correction circuit of claim 9 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; hold register means for storing a hold signal H i ; second PES logic means coupled to said flag means and to said hold register means for setting said flag signal F i =1 and for setting said hold signal H i =y i *sign(y i-1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0); and third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (y i *sign(y i+1 )-H i-1 ) and for resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(0,0,1).

Claim 14

Dependent Claim 141 words

The clock phase error correction circuit of claim 9 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; second PES logic means coupled to said flag means for setting said flag signal F i =1 responsive to a digital code sequence (d i-1 , d i , d i+1 )=(0,0,1); third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (y i-2 -y i )*sign(y i-1 ) and resetting said flag signal F i =0 responsive to a detector code sequence d i-1 , d i , d i+1 )=(1,0,0); and reset means in said first PES logic means for resetting said flag signal F i =0 responsive to said detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Claim 15

Dependent Claim 222 words

In a direct access storage device (DASD) having a processing channel for recovering coded binary data from an analog signal representing data stored as a plurality of signal transitions in said DASD, a clock phase error correction circuit comprising: converter means coupled to said sampling means and to said clock means for producing multiplicity or digital signals {y i } representing said sequential samples {S i }; register means coupled to said converter means for storing a sequence of at least three said digital signals (y i-1 , y i , y i+1 ); peak detector means coupled to said register means for encoding each said sequence of digital signals to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; error means coupled to said peak detector means for producing a digital clock phase error signal (PES) e i in response to each sequence of at least three adjacent said detector codes (d i-1 , d i , d i+1 ); and phase adjusting means coupled to said error means and to said clock means for adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 16

Dependent Claim 222 words

In a direct access storage device (DASD) having a processing channel for recovering coded binary data from an analog signal representing data stored as a plurality of signal transitions in said DASD, a clock phase error correction circuit comprising: converter means coupled to said sampling means and to said clock means for producing multiplicity or digital signals {y i } representing said sequential samples {S i }; register means coupled to said converter means for storing a sequence of at least three said digital signals (y i-1 , y i , y i+1 ); peak detector means coupled to said register means for encoding each said sequence of digital signals to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; error means coupled to said peak detector means for producing a digital clock phase error signal (PES) e i in response to each sequence of at least three adjacent said detector codes (d i-1 , d i , d i+1 ); and phase adjusting means coupled to said error means and to said clock means for adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 17

Dependent Claim 138 words

The DASD channel clock phase error correction circuit of claim 13 wherein said peak detector means further comprises: logic means for comparing said three sequential digital signals (y i-1 , y i , y i+1 ) and for selecting said digital detector code d i such that, if (y i >y i-1 ) and (y i ≧y i+1 ) and (y i >k + ) or (y i <y i-1 ) and (y i ≦y i+1 ) and (y i <k - ), wherein k + and k - are predetermined threshold values, said digital detector code d i =1 indicating the occurrence of an analog signal extremum near said signal sample S i , otherwise said digital detector code d i =0 indicating no occurrence of an analog signal extremum near said signal sample S i .

Claim 18

Dependent Claim 50 words

The DASD channel clock phase error correction circuit of claim 14 wherein said peak logic means further comprises: first PES logic means for producing a digital clock PES e i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Claim 19

Dependent Claim 150 words

The DASD channel clock phase error correction circuit of claim 15 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; hold register means for storing a hold signal H i ; second PES logic means coupled to said flag means and to said hold register means for setting said flag signal F i =1 and for setting said hold signal H i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(0,0,1); and third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (H i-1 -y i *sign(y i-1 )) and for resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=1,0,0).

Claim 20

Dependent Claim 150 words

The DASD channel clock phase error correction circuit of claim 15 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; hold register means for storing a hold signal H i ; second PES logic means coupled to said flag means and to said hold register means for setting said flag signal F i =1 and for setting said hold signal H i =y i *sign(y i-1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0); and third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (y i *sign(y i+1 )-H i-1 ) and for resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(0,0,1).

Claim 21

Dependent Claim 141 words

The DASD channel clock phase error correction circuit of claim 15 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; second PES logic means coupled to said flag means for setting said flag signal F i =1 responsive to a digital code sequence (d i-1 , d i , d i+1 )=(0,0,1); third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (y i-2 -y i )*sign(y i-1 ) and resetting said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0); and reset means in said first PES logic means for resetting said flag signal F=0 responsive to said detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Claim 22

Dependent Claim 266 words

In an optical data storage device having a processing channel for recovering coded binary data from an analog signal represented data stored as a plurality of signal transitions in said optical data storage device, said channel having clock means for generating a channel clock signal and sampling means for sampling said analog signal to produce a plurality of sequential signal samples {S i } responsive to said channel clock signal, wherein i is an integer, a clock phase error correction circuit comprising: converter means coupled to said sampling means and to said clock means for producing a multiplicity of digital signals {y i } representing said sequential samples {S i }; register means coupled to said converter means for storing a sequence of at least three said digital signals (y i-1 , y i , y i+1 ); peak detector means coupled to said register means for encoding each said sequence of digital signals to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; error means coupled to said peak detector means for producing a digital clock phase error signal (PES) e i in response to each sequence of at least three adjacent said detector codes (d i-1 , d i , d i+1 ); and phase adjusting means coupled to said error means and to said clock means for adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 23

Dependent Claim 266 words

In an optical data storage device having a processing channel for recovering coded binary data from an analog signal represented data stored as a plurality of signal transitions in said optical data storage device, said channel having clock means for generating a channel clock signal and sampling means for sampling said analog signal to produce a plurality of sequential signal samples {S i } responsive to said channel clock signal, wherein i is an integer, a clock phase error correction circuit comprising: converter means coupled to said sampling means and to said clock means for producing a multiplicity of digital signals {y i } representing said sequential samples {S i }; register means coupled to said converter means for storing a sequence of at least three said digital signals (y i-1 , y i , y i+1 ); peak detector means coupled to said register means for encoding each said sequence of digital signals to produce a digital detector code d i having one of at least two values representing whether or not an extremum occurs in said analog signal near the signal sample S i corresponding to said each digital signal y i ; error means coupled to said peak detector means for producing a digital clock phase error signal (PES) e i in response to each sequence of at least three adjacent said detector codes (d i-1 , d i , d i+1 ); and phase adjusting means coupled to said error means and to said clock means for adjusting said channel clock signal phase responsive to said digital clock PES e i .

Claim 24

Dependent Claim 139 words

The optical data storage device clock phase error correction circuit of claim 19 wherein said peak detector means further comprises: logic means for comparing said three sequential digital signals (y i-1 , y i , y i+1 ) and for selecting said digital detector code d i such that, if (y i >y i-1 ) and (y i ≧y i+1 ) and (y i >k + ) or (y i <y i-1 ) and (y i ≦y i+1 ) and (y i <k - ), wherein k + and k - are predetermined threshold values, said digital detector code d i =1 indicating the occurrence of an analog signal extremum near said signal S i , otherwise said digital detector code d i =0 indicating no occurrence of an analog signal extremum near said signal sample S i .

Claim 25

Dependent Claim 52 words

The optical data storage channel clock phase error correction circuit of claim 20 wherein said peak logic means further comprises: first PES logic means for producing a digital clock PES e i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Claim 26

Dependent Claim 152 words

The optical data storage channel clock phase error correction circuit of claim 21 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; hold register means for storing a hold signal H i ; second PES logic means coupled to said flag means and to said hold register means for setting said flag signal F i =1 and for setting said hold signal H i =y i *sign(y i+1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(0,0,1); and third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (H i-1 -y i *sign(y i-1 )) and for resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0).

Claim 27

Dependent Claim 152 words

The optical data storage channel clock phase error correction circuit of claim 21 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; hold register means for storing a hold signal H i ; second PES logic means coupled to said flag means and to said hold register means for setting said flag signal F i =1 and for setting said hold signal H i =y i *sign(y i-1 ) responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0); and third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (y i *sign(y i+1 )-H i-1 ) and for resetting said hold signal H i =0 and said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(0,0,1).

Claim 28

Dependent Claim 145 words

The optical data storage channel clock phase error correction circuit of claim 21 wherein said peak logic means further comprises: flag means for storing a flag signal F i ; second PES logic means coupled to said flag means for setting said flag signal F i =1 responsive to a digital code sequence (d i- , d i , d i+1 )=(0,0,1); third PES logic means coupled to said second PES logic means for producing a digital clock PES e i =F i-1 (y i-2 -y i )*sign(y i-1 ) and resetting said flag signal F i =0 responsive to a detector code sequence (d i-1 , d i , d i+1 )=(1,0,0); and reset means in said first PES logic means for resetting said flag signal F i =0 responsive to said detector code sequence (d i-1 , d i , d i+1 )=(1,0,1).

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-09-24	2000-03-25	2000-09-24	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-09-24	2004-03-25	2004-09-24	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-09-24	2008-03-25	2008-09-24	$7700.00	Window Closed / Lapsed

Digital timing recovery method and apparatus for a coded data channel

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