Clock delay trim adjustment with stopping feature for eliminating differential delay between clock signal and analog signal

Claim 3

The method of claim 1, wherein a sample qualifies as a peak when its magnitude exceeds a predetermined value and is not smaller than the magnitude of both immediately preceding and immediately following samples.

Claim 6

The method of claim 3, including following step (d), the steps of: resetting said counters to zero; and returning to steps (b), (c) and (d).

Claim 7

The method of claim 3, including the step of: (e) terminating adjustment of phase during step (b), (c) or (d) if the first counter counts a predetermined number (N 2 ) of qualified events.

Claim 8

The method of claim 5, including the steps of: (f) with a third counter (C), counting how often two adjacent samples exceed said predetermined value; (g) adjusting the phase a preselected greater amount in a direction controlled by said current sign indicated by said second counter irrespective of the count in said second counter whenever the count of the third counter exceeds a predetermined threshold (T 3 ); and (h) following steps (d) or (g), resetting said first, second and third counters, and returning to steps (b) (c) and (d).

Claim 9

The method of claim 3, including in step (d) the step of: adjusting the phase said preselected amount in the direction controlled by said current sign when the count in the second counter reaches (i) either of two limits of a predetermined smaller range (T 1 to -T 1 ) symmetrically contained within a predetermined larger range (T 2 to -T 2 ) before the count in said first count exceeds a predetermined number (N 1 ).

Claim 10

Circuitry for phase synchronizing an analog input signal with a clock signal, comprising: a delay element initially having an arbitrary delay setting; means for converting the analog signal into a series of digitized samples at successive clock signals; means for comparing the relative values of three successive samples for determining whether the value of the second sample qualifies as a peak; means for comparing the relative values of the first sample and third sample for generating an error signal denoting positive or negative direction of a phase error event; and means responsive to said error signal for adjusting the delay setting toward a correct setting for correspondingly adjusting the phase differential of the clock and analog input signal toward synchronization.

Claim 11

Circuitry for phase synchronizing an analog input signal with a clock signal, comprising: a delay element initially having an arbitrary delay setting; means for converting the analog signal into a series of digitized samples at successive clock signals; means for comparing the relative values of three successive samples for determining whether the value of the second sample qualifies as a peak; means for comparing the relative values of the first sample and third sample for generating an error signal denoting positive or negative direction of a phase error event; and means responsive to said error signal for adjusting the delay setting toward a correct setting for correspondingly adjusting the phase differential of the clock and analog input signal toward synchronization.

Claim 12

The circuitry of claim 8, wherein a sample qualifies as a peak when its magnitude exceeds a predetermined value and is not smaller than the magnitudes of both immediately preceding and immediately following samples.

Claim 13

Circuitry for phase synchronizing an analog input signal with a clock signal, comprising: p1 an analog-to-digital converter for converting, at successive clock signals, the analog signal into a series of digitized samples which may be subject to noise; a first counter (A) for counting qualified events identified by a sample having a magnitude exceeding a predetermined value K and not smaller than the magnitudes of both the immediately preceding and immediately following samples; a second counter (B) for generating, from a sequence of qualified events, a count of phase error events with positive direction and those with negative direction and cumulatively indicating numerical difference therebetween by a current signal and weight of the phase error events; and means responsive to the count in the second counter reaching preselected limits for adjusting the phase a preselected amount in a direction controlled by said current sign.

Claim 14

Circuitry for phase synchronizing an analog input signal with a clock signal, comprising: p1 an analog-to-digital converter for converting, at successive clock signals, the analog signal into a series of digitized samples which may be subject to noise; a first counter (A) for counting qualified events identified by a sample having a magnitude exceeding a predetermined value K and not smaller than the magnitudes of both the immediately preceding and immediately following samples; a second counter (B) for generating, from a sequence of qualified events, a count of phase error events with positive direction and those with negative direction and cumulatively indicating numerical difference therebetween by a current signal and weight of the phase error events; and means responsive to the count in the second counter reaching preselected limits for adjusting the phase a preselected amount in a direction controlled by said current sign.

Claim 15

The circuitry of claim 10, including means operative when the count in said second counter reaches one of said preselected limits for resetting said counters to zero.

Claim 16

The circuitry of claim 10, including means responsive to the first counter counting a predetermined number (N 2 ) of qualified events for disabling said adjusting means.

Claim 17

Circuitry for phase synchronizing an analog input signal with a clock signal comprising: a delay element initially having an arbitrary delay setting; an analog-to-digital converter (ADC) responsive to successive clock signals for converting the analog signal into a series of digitized samples subject to noise; and clock delay trim adjustment circuitry connected to the output of the ADC and providing an input to the delay element, said adjustment circuitry comprising: (a) a first counter (A) for qualified events identified by a sample having a magnitude exceeding a predetermined value (K) and not smaller than the magnitudes of both the immediately preceding and immediately following samples; (b) a second counter (B) for generating from a series of qualified events a count of phase error events with positive direction and those with negative direction and cumulatively indicating numerical difference therebetween by a current sign and weight of phase error events; (c) a third counter (C) for counting how often two adjacent samples have a magnitude exceeding the predetermined value (K); (d) first means for bumping a delay setting up or down a preselected amount when the count in the second counter reaches a preestablished threshold value (e.g., T 1 or -T 1 ) before the count in the first counter exceeds a preestablished number (e.g., N 1 ); and (e) second means operative, whenever the count in the third counter reaches a preselected threshold (T 3 ), for bumping the delay setting a preselected greater amount up or down depending upon the sign of the count in the second counter for insuring against hunting.

Claim 18

Circuitry for phase synchronizing an analog input signal with a clock signal comprising: a delay element initially having an arbitrary delay setting; an analog-to-digital converter (ADC) responsive to successive clock signals for converting the analog signal into a series of digitized samples subject to noise; and clock delay trim adjustment circuitry connected to the output of the ADC and providing an input to the delay element, said adjustment circuitry comprising: (a) a first counter (A) for qualified events identified by a sample having a magnitude exceeding a predetermined value (K) and not smaller than the magnitudes of both the immediately preceding and immediately following samples; (b) a second counter (B) for generating from a series of qualified events a count of phase error events with positive direction and those with negative direction and cumulatively indicating numerical difference therebetween by a current sign and weight of phase error events; (c) a third counter (C) for counting how often two adjacent samples have a magnitude exceeding the predetermined value (K); (d) first means for bumping a delay setting up or down a preselected amount when the count in the second counter reaches a preestablished threshold value (e.g., T 1 or -T 1 ) before the count in the first counter exceeds a preestablished number (e.g., N 1 ); and (e) second means operative, whenever the count in the third counter reaches a preselected threshold (T 3 ), for bumping the delay setting a preselected greater amount up or down depending upon the sign of the count in the second counter for insuring against hunting.

Claim 19

The circuitry of claim 13, including means for terminating adjustment of the delay setting when the count in said first counter reaches a preselected number (N 2 ).

Claim 20

The circuitry of claim 13, including means for resetting said counters whenever the count in said second counter reaches the preestablished threshold value.

Claim 21

The circuitry of claim 15, including a delay settle counter which counts clock cycles for delaying operations of said resetting means for a predetermined number of clock cycles after each bumping operation of said first means or second means.

Claim 22

The circuitry of claim 13, wherein the second counter has four preestablished threshold values T 1 , -T 1 , T 2 , and -T 2 , the values T 1 being smaller than that of T 2 and wherein said first bumping means bumps the delay setting up or down the preselected amount when the count in the second counter reaches either (i) +T 1 or -T 1 respectively, before the count in the first counter exceeds N 1 , or (ii) +T 2 or -T 2 respectively, after N 1 is reached, but before a preestablished larger number N 2 is reached at which the delay setting is presumed correct.

Claim 23

The circuitry of claim 13, including a controller for enabling the clock delay trim adjustment circuitry only for a preselected number of cycles of a run length limited high frequency data pattern read from a data storage medium during a preselected period of operation for estimating phase error over a preselected number of sample values deemed sufficient to eliminate noise effect, and disabling the trim adjustment circuitry when trim adjustment is completed.