Clock controller employing a discrete time control loop method for clocking data in an asynchronous channel

Claim 2

In a Direct Access Storage Device (DASD) having a recording channel for recovering data (D) stored as a plurality of signal transitions in said DASD, an asynchronous discrete clock controller having an asynchronous sampling clock frequency F s , where a normalized clock frequency F i is defined as the ratio of a synchronous data clock frequency F d to said sampling clock frequency F s , where i is a non-zero positive integer and 0≦a,b≦1, said clock controller comprising: output bus means for delivering said recovered data (D); input means for receiving a first digital word representing the detection time P i of an i th said signal transition; first multiplier means coupled to said input means for multiplying said first digital word P i by a second digital word representing said normalized clock frequency F i to create a third digital word representing a normalized transition detection value P' i =P i F i ; phase error correction means coupled to said first multiplier means for adding said third digital word P' i to a fourth digital word representing a once-delayed value of a weighted phase error aE' i-1 to create a fifth digital word representing a corrected transition detection value Z' i =P' i +aE' i-1 said fifth digital word having a rounded integral value representing an i th said datum D i =RND(Z' i ), wherein the fractional difference between said fifth digital word and said rounded integral value represents a normalized phase error E' i =Z' i -D i of said normalized transition detection value P i ; and output means coupled to said phase error correction means for rounding said fifth digital word Z' i to create said datum D i =RND(Z' i ) and for presenting said datum D i to said output bus means.

Claim 3

The DASD clock controller of claim 1 wherein said phase error correction means further comprises: first register means for storing said fractional difference E i '=Z i '-D i of said fifth digital word Z i '; first delay means coupled to said first register means for storing a once delayed said fractional difference representing a once-delayed value for said estimated normalized error E i-1 ' of an earlier said fifth digital word Z i-1 '; and second multiplier means coupled to said first delay means for multiplying said once-delayed fractional difference E i-1 ' by a first digital constant (a) to generate said fourth digital word representing said weighted normalized phase error aE' i-1 .

Claim 4

The DASD clock controller of claim 2 further comprising: second register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and third multiplier means coupled to said second register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a two-parameter weighted frequency error (1-bE' i ) to create said second digital word representing said normalized clock frequency F i =(1-bE' i )F i-1 .

Claim 5

The DASD clock controller of claim 2 further comprising: second register means for storing an earlier said second 4 digital word representing a once-delayed said normalized clock frequency F i-1 ; and third multiplier means coupled to said second register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a three-parameter weighted frequency error [1-b(E' i +aE i-1 ')] to create said second digital word representing said normalized clock frequency F i =[1-b(E' i +aE' i-1 )]F i-1 .

Claim 6

The DASD clock controller of claim 1 further comprising: register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and second multiplier means coupled to said register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a two-parameter weighted frequency error (1-bE' i ) to create said second digital word representing said normalized clock frequency F i =(1-bE' i )F i-1 .

Claim 7

The DASD clock controller of claim 1 further comprising: register means for storing an earlier said second digital word representing of a once-delayed said normalized clock frequency F i-1 ; and second multiplier means coupled to said register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a three-parameter weighted frequency error [1-b(E' i +aE' i-1 )] to create said second digital word representing said normalized clock frequency F i =[1-b(E' i +aE' i-1 )]F i-1 .

Claim 8

In an optical data storage device having a recording channel for recovering data (D) stored as a plurality of signal transitions in said optical data storage device, an asynchronous discrete clock controller having an asynchronous sampling clock frequency F s , where a normalized clock frequency F i is defined as the ratio of a synchronous data clock frequency F d to said sampling clock frequency F s , where i is a non-zero positive integer and 0≦a,b≦1, said clock controller comprising: output bus means for delivering said recovered data (D); input means for receiving a first digital word representing the detection time P i of an i th said signal transition; first multiplier means coupled to said input means for multiplying said first digital word P i by a second digital word representing said normalized clock frequency F i to create a third digital word representing a normalized transition detection value P' i =P i F i ; phase error correction means coupled to said first multiplier means for adding said third digital word P' i to a fourth digital word representing a once-delayed value of a weighted phase error aE' i-1 to create a fifth digital word representing a corrected transition detection value Z' i =P' i +aE' i-1 , said fifth digital word having a rounded integral value representing an i th said datum D i =RND(Z' i ), wherein the fractional difference between said fifth digital word and said rounded integral value represents a normalized phase error E' i =Z' i -D i of said normalized transition detection value P i ; and output means coupled to said phase error correction means for rounding said fifth digital word Z' i to create said datum D i =RND(Z' i ) and for presenting said datum D i to said output bus means.

Claim 9

In an optical data storage device having a recording channel for recovering data (D) stored as a plurality of signal transitions in said optical data storage device, an asynchronous discrete clock controller having an asynchronous sampling clock frequency F s , where a normalized clock frequency F i is defined as the ratio of a synchronous data clock frequency F d to said sampling clock frequency F s , where i is a non-zero positive integer and 0≦a,b≦1, said clock controller comprising: output bus means for delivering said recovered data (D); input means for receiving a first digital word representing the detection time P i of an i th said signal transition; first multiplier means coupled to said input means for multiplying said first digital word P i by a second digital word representing said normalized clock frequency F i to create a third digital word representing a normalized transition detection value P' i =P i F i ; phase error correction means coupled to said first multiplier means for adding said third digital word P' i to a fourth digital word representing a once-delayed value of a weighted phase error aE' i-1 to create a fifth digital word representing a corrected transition detection value Z' i =P' i +aE' i-1 , said fifth digital word having a rounded integral value representing an i th said datum D i =RND(Z' i ), wherein the fractional difference between said fifth digital word and said rounded integral value represents a normalized phase error E' i =Z' i -D i of said normalized transition detection value P i ; and output means coupled to said phase error correction means for rounding said fifth digital word Z' i to create said datum D i =RND(Z' i ) and for presenting said datum D i to said output bus means.

Claim 10

The optical data storage device clock controller of claim 7 further comprising: first register means for storing said fractional difference E' i =Z' i -D i of said fifth digital word Z' i ; first delay means coupled to said first register means for storing a once-delayed said fractional difference representing a once-delayed value for said estimated normalized error E' i-1 of an earlier said fifth digital word Z' i-1 ; and second multiplier means coupled to said first, delay means for multiplying said once-delayed fractional difference E' i-1 by a first digital constant (a) to generate said fourth digital word representing said weighted normalized phase error aE' i-1 .

Claim 11

The optical data storage device clock controller of claim 4 further comprising: second register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and third multiplier means coupled to said second register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a two-parameter weighted frequency error (1-bE' i ) to create said second digital word representing said normalized clock frequency F i =(1-bE' i )F i-1 .

Claim 12

The optical data storage device clock controller of claim 8 further comprising: second register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and third multiplier means coupled to said second register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a three-parameter weighted frequency error [1-b(E' i +aE' i-1 )] to create said second digital word representing said normalized clock frequency F i =[1-b(E' i +aE' i-1 )]F i-1 .

Claim 13

The optical data storage device clock controller of claim 1 further comprising: register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and second multiplier means coupled to said register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a two-parameter weighted frequency error (1-bE' i ) to create said second digital word representing said normalized clock frequency F i =(1-bE' i )F i-1 .

Claim 14

The optical data storage device clock controller of claim 7 further comprising: register means for storing an earlier said second digital word representing of a once-delayed said normalized clock frequency F i-1 ; and second multiplier means coupled to said register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a three-parameter weighted frequency error [1-b(E' i +aE' i-1 )] to create said second digital word representing said normalized clock frequency F i =[1-b(E' i +aE' i-1 )]F i-1 .

Claim 15

In a data storage tape drive having a recording channel for recovering data (D) stored as a plurality of signal transitions in said tape drive media, an asynchronous discrete clock controller having an asynchronous sampling clock frequency F s , where a normalized clock frequency F i is defined as the ratio of a synchronous data clock frequency F d to said sampling clock frequency F s , where i is a non-zero positive integer and 0≦a,b≦1, said clock controller comprising: output bus means for delivering said recovered data (D); input means for receiving a first digital word representing the detection time P i of an i th said signal transition; first multiplier means coupled to said input means for multiplying said first digital word P i by a second digital word representing said normalized clock frequency F i to create a third digital word representing a normalized transition detection value P' i =P i F i ; phase error correction means coupled to said first multiplier means for adding said third digital word P' i to a fourth digital word representing a once-delayed value of a weighted phase error aE' i-1 to create a fifth digital word representing a corrected transition detection value Z' i =P' i +aE' i-1 , said fifth digital word having a rounded integral value representing an i th said datum D i =RND(Z' i ), wherein the fractional difference between said fifth digital word and said rounded integral value represents a normalized phase error E' i =Z' i -D i of said normalized transition detection value P i ; and output means coupled to said phase error correction means for rounding said fifth digital word Z' i to create said datum D i =RND(Z' i ) and for presenting said datum D i to said output bus means.

Claim 16

In a data storage tape drive having a recording channel for recovering data (D) stored as a plurality of signal transitions in said tape drive media, an asynchronous discrete clock controller having an asynchronous sampling clock frequency F s , where a normalized clock frequency F i is defined as the ratio of a synchronous data clock frequency F d to said sampling clock frequency F s , where i is a non-zero positive integer and 0≦a,b≦1, said clock controller comprising: output bus means for delivering said recovered data (D); input means for receiving a first digital word representing the detection time P i of an i th said signal transition; first multiplier means coupled to said input means for multiplying said first digital word P i by a second digital word representing said normalized clock frequency F i to create a third digital word representing a normalized transition detection value P' i =P i F i ; phase error correction means coupled to said first multiplier means for adding said third digital word P' i to a fourth digital word representing a once-delayed value of a weighted phase error aE' i-1 to create a fifth digital word representing a corrected transition detection value Z' i =P' i +aE' i-1 , said fifth digital word having a rounded integral value representing an i th said datum D i =RND(Z' i ), wherein the fractional difference between said fifth digital word and said rounded integral value represents a normalized phase error E' i =Z' i -D i of said normalized transition detection value P i ; and output means coupled to said phase error correction means for rounding said fifth digital word Z' i to create said datum D i =RND(Z' i ) and for presenting said datum D i to said output bus means.

Claim 17

The optical data storage device clock controller of claim 13 further comprising: first register means for storing said fractional difference E' i =Z' i -D i of said fifth digital word Z' i ; first delay means coupled to said first register means for storing a once-delayed said fractional difference representing a once-delayed value for said estimated normalized error E' i-1 of an earlier said fifth digital word Z' i-1 ; and second multiplier means coupled to said first delay means for multiplying said once-delayed fractional difference E' i-1 by a first digital constant (a) to generate said fourth digital word representing said weighted normalized phase error aE' i-1 .

Claim 18

The optical data storage device clock controller of claim 14 further comprising: second register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and third multiplier means coupled to said second register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a two-parameter weighted frequency error (1-bE' i ) to create said second digital word representing said normalized clock frequency F i =(1-bE' i )F i-1 .

Claim 19

The optical data storage device clock controller of claim 14 further comprising: second register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and third multiplier means coupled to said second register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a three-parameter weighted frequency error [1-b(E' i +aE' i-1 )] to create said second digital word representing said normalized clock frequency F i =[1-b(E' i +aE' i-1 )]F i-1 .

Claim 20

The optical data storage device clock controller of claim 13 further comprising: register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and second multiplier means coupled to said register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a two-parameter weighted frequency (1-bE' i ) to create said second digital word representing said normalized clock frequency F i =(1-bE' i )F i-1 .

Claim 21

The optical data storage device clock controller of claim 13 further comprising: register means for storing an earlier said second digital word representing a once-delayed said normalized clock frequency F i-1 ; and second multiplier means coupled to said register means for multiplying said stored second digital word F i-1 by a sixth digital word representing a three-parameter weighted frequency error [1-b(E' i +aE' i-1 )] to create said second digital word representing said normalized clock frequency F i =[1-b(E' i +aE' i-1 )]F i-1 .