US3882540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Readback circuits for digital signal recorders
Assignee: International Business Machines Corp
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Filing: 1974-06-17
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Granted: 1975-05-06
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Expires: 1994-06-17
Abstract
Abstract Digital signal processing techniques enhance readback of digital signals from a magnetic recorder. Sampled signal amplitudes obtained at bit period boundaries and midpoints are converted to digital signal sets, which sets are processed for equalization, DC restoration, phase error detection, generation of timing signals, and amplitude compensation of the sampled signal amplitudes.
Inventors
- 👤 Hjalmar H Ottesen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:32
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10203; G11B20/10037; G11B20/14; G11B20/1403; G11B5/00; G11B5/02; G11B5/027; G11B5/035
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
263 words
A readback circuit for a digital signal recorder, sensing means for generating a readback signal having periodic bit periods T, the improvement including in combination: sample and hold means receiving said readback signal and holding sampled signal amplitudes; a digital-to-analog converter circuit (DAC) for repeatedly converting said held sampled signal amplitudes to first sets of digital signals, each set including a sign signal; a gated DAC register receiving said first set of digital signals; a first digital signal processing circuit receiving said first sets of digital signals and operative to generate second sets of digital signals, each including a sign signal, based upon said first sets of digital signals in accordance with a given transfer function; timing means responsive to successive ones of said second sets of digital signals to adjust its operation to supply timing signals in accordance with said bit periods T; said sample and hold means responsive to said timing signals to receive said readback signal at least at bit period boundaries; said timing signals actuating said gated DAC register to receive said first sets of digital signals after each receipt of said readback signal amplitudes by said sample and hold means and further actuating said digital signal processing circuit to operate synchronously with said bit periods; digital-to-analog converter means responsive to said second sets of digital signals to supply a bias signal related to a magnitude represented by successive ones of said second sets of digital signals; and means in said sample and hold means responsive to said bias signal to adjust said sampled signal amplitude in accordance therewith.
Claim 2
Dependent Claim
263 words
A readback circuit for a digital signal recorder, sensing means for generating a readback signal having periodic bit periods T, the improvement including in combination: sample and hold means receiving said readback signal and holding sampled signal amplitudes; a digital-to-analog converter circuit (DAC) for repeatedly converting said held sampled signal amplitudes to first sets of digital signals, each set including a sign signal; a gated DAC register receiving said first set of digital signals; a first digital signal processing circuit receiving said first sets of digital signals and operative to generate second sets of digital signals, each including a sign signal, based upon said first sets of digital signals in accordance with a given transfer function; timing means responsive to successive ones of said second sets of digital signals to adjust its operation to supply timing signals in accordance with said bit periods T; said sample and hold means responsive to said timing signals to receive said readback signal at least at bit period boundaries; said timing signals actuating said gated DAC register to receive said first sets of digital signals after each receipt of said readback signal amplitudes by said sample and hold means and further actuating said digital signal processing circuit to operate synchronously with said bit periods; digital-to-analog converter means responsive to said second sets of digital signals to supply a bias signal related to a magnitude represented by successive ones of said second sets of digital signals; and means in said sample and hold means responsive to said bias signal to adjust said sampled signal amplitude in accordance therewith.
Claim 3
Dependent Claim
55 words
The readback circuit set forth in claim 1 wherein said digital signal processing circuit includes a first digital signal processing portion which is a bilinear Z transformation of an analog equalizing circuit and a second digital signal processing portion together effecting an equalizing and a DC restore function on said first sets of digital signals.
Claim 4
Dependent Claim
155 words
The readback circuit set forth in claim 1 further including a feedback digital Signal processing circuit converting said second sets of digital signals to absolute magnitude sets, digital signal processing low pass filter means responsive to said feedback digital signal processing circuit to supply a readback signal envelope indicating set of digital signals, digital signal DC restore circuit in said first digital signal processing circuit receiving said signal envelope indicating set of digital signals and converting same to a second absolute magnitude set of digital signals, scaling means in said digital signal DC restore circuit for receiving said second absolute magnitude set of digital signals to produce a DC restore set of digital signals, and adder means in said digital signal DC restore circuit for combining said DC restore set of digital signals with corresponding sets of digital signals derived from said first set of digital signals to produce said second set of digital signals.
Claim 5
Dependent Claim
167 words
The readback circuit set forth in claim 3 wherein said signal sets have N-binary signals and said first digital signal processing circuit includes a digital signal equalizing circuit receiving said first sets of digital signals to generate said corresponding sets of digital signals wherein said digital signal equalizing circuit is a Z transformation of an analog equalizing circuit and comprising; a first signal path means for processing said first sets of digital signals in accordance with a predetermined multiplicative function to produce N-bit partial equalized sets of digital signals, a plurality of second signal path means each for processing said first sets of digital signals each in accordance with multiplicative and summation of 2N bit intermediate signal sets and each said second path means having an output multiplicative means for performing a predetermined N-bit multiplicative function to produce additional N-bit partial equalized sets of digital signals, and N-bit adder means combining said N-bit partial equalized signal sets of digital signals into said corresponding sets of digital signals.
Claim 6
Dependent Claim
45 words
The readback circuit set forth in claim 4 further including digital data detector means receiving said second sets of digital signals and responsive to said timing signals to sense sign changes in said second sets of digital signals to indicate data in said readback signal.
Claim 7
Dependent Claim
192 words
A readback circuit for a magnetic record medium storing digital-like signals, means for sensing said stored signals and supplying an analog-type readback signal representative of said sensed stored signals, the improvement including in combination: a sample and hold circuit receiving said readback signal and holding sampled amplitudes, an analog-to-digital converter for converting said held sampled amplitudes to a set of signed parallel digital signals, first digital signal processing circuit means receiving said parallel digital signals and processing same in accordance with a predetermined transfer function to produce a second set of signed digital signals, feedback means receiving said second set of digital signals including a digital-to-analog converter for supplying an analog feedback signal derived from said second set of digital signals, said sample and hold circuit including analog gain adjust means responsive to said analog feedback signal to adjust said received signal amplitudes in accordance therewith, and a timing signal generator responsive to said second set of digital signals to supply timing signals slaved to said readback signal for timing said sample and hold circuit to receive said readback signals at predetermined sample times and for timing said digital signal processing circuits.
Claim 8
Dependent Claim
192 words
A readback circuit for a magnetic record medium storing digital-like signals, means for sensing said stored signals and supplying an analog-type readback signal representative of said sensed stored signals, the improvement including in combination: a sample and hold circuit receiving said readback signal and holding sampled amplitudes, an analog-to-digital converter for converting said held sampled amplitudes to a set of signed parallel digital signals, first digital signal processing circuit means receiving said parallel digital signals and processing same in accordance with a predetermined transfer function to produce a second set of signed digital signals, feedback means receiving said second set of digital signals including a digital-to-analog converter for supplying an analog feedback signal derived from said second set of digital signals, said sample and hold circuit including analog gain adjust means responsive to said analog feedback signal to adjust said received signal amplitudes in accordance therewith, and a timing signal generator responsive to said second set of digital signals to supply timing signals slaved to said readback signal for timing said sample and hold circuit to receive said readback signals at predetermined sample times and for timing said digital signal processing circuits.
Claim 9
Dependent Claim
47 words
The readback circuit set forth in claim 6 wherein said feedback means includes digital signal absolute magnitude means for converting each said set of second digital signals to an absolute magnitude set of digital signals, and said digital-to-analog converter rEceiving said absolute magnitude set of digital signals.
Claim 10
Dependent Claim
67 words
The readback circuit set forth in claim 7 wherein said first digital signal processing circuit means includes a portion responsive to signal envelope indicating sets of digital signals for altering the effect of said predetermined transfer function in accordance therewith, digital signal processing low pass filter means receiving said absolute magnitude set of digital signals for correcting same to said signal envelope indicating set of digital signals.
Claim 11
Independent Claim
118 words
The method of extracting data from a periodic readback signal derived from a record medium, the steps of: correcting said readback signal into successive sets of first signed digital signals representative of readback signal amplitude and polarity at predetermined signal points including adjacent zero-crossover points, processing said first signal sets in accordance with a predetermined transfer function to produce corresponding second signed sets of digital signals, combining successive ones of said second signed sets of digital signals to produce timing pulses related to said periodic readback signal, timing said converting and processing steps in accordance with said timing pulses, and indicating data in accordance with predetermined successive ones of said second sets in accordance with said timing pulses.
Claim 12
Independent Claim
118 words
The method of extracting data from a periodic readback signal derived from a record medium, the steps of: correcting said readback signal into successive sets of first signed digital signals representative of readback signal amplitude and polarity at predetermined signal points including adjacent zero-crossover points, processing said first signal sets in accordance with a predetermined transfer function to produce corresponding second signed sets of digital signals, combining successive ones of said second signed sets of digital signals to produce timing pulses related to said periodic readback signal, timing said converting and processing steps in accordance with said timing pulses, and indicating data in accordance with predetermined successive ones of said second sets in accordance with said timing pulses.
Claim 13
Dependent Claim
41 words
The method set forth in claim 9 having the steps of generating an analog indication of an absolute magnitude of given successive ones of said second sets of digital signals, and adjusting said converting step in accordance with said analog indication.
References Cited (Backward Citations)
US3623040A
Cited
US3821716A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |