Intelligent snoopy bus arbiter

Claim 1

In a multiprocessor system including a plurality of processors coupled via a system bus to a main memory the system bus operating in accordance with a SNOOPY bus protocol, each processor having a cache memory that is accessible by the respective processor and is accessible by the other processors in said multiprocessor system via transactions on the system bus, each transaction including the communication of address and data information over the system bus, a method of ensuring adequate access to said cache by said respective processor to prevent starvation of said respective processor, said method comprising the steps of: arbitrating between requests for access to said system bus by said plurality of processors, said step of arbitrating further comprising the steps of; monitoring the system bus for a preselected pattern of transaction activity on the bus, wherein the step of monitoring the bus for a preselected pattern of transaction activity comprises the step of monitoring the bus to detect a preselected number of back-to-back bus write transactions; and upon detecting the preselected pattern of transaction activity by said monitoring, inserting an idle bus cycle on said system bus to permit said respective processor to access its cache memory.