Built-in self-test for logic circuitry at memory array output

Claim 3

The system of claim 1, wherein said means for providing said test pattern to said logic circuitry includes a multiplexer circuit connected to said memory array and to said BIST for writing said portion of said test pattern into said memory array as directed by said BIST.

Claim 4

The system of claim 2, wherein said logic circuitry comprises a two input logic circuit having a port A input and a port B input, said port A input being electrically coupled to an output port of said memory array and said port B input being electrically coupled to said BIST, and wherein said portion of said test pattern written into said memory array comprises a first portion of said test pattern, and wherein said means for providing said test pattern to said logic circuitry further includes means for applying a second portion of said test pattern to said port B input of said logic circuitry without employing said memory array.

Claim 5

The system of claim 3, wherein said first portion of said test pattern comprises a looping test pattern consisting of a shifting 1 bit in a field of 0 bits or a shifting 0 bit in a field of 1 bits, and wherein said means for providing said first portion of said test pattern to said memory array includes an input shift register electrically coupled between said memory array and said BIST, said input shift register having multiple latches and a feedback path from an end latch in the input shift register to a first latch in the input shift register such that contents of the input shift register automatically loop with shifting of said 1 bit in said field of 0 bits or said 0 bit in said field of 1 bits.

Claim 6

The system of claim 3, wherein said second portion of said test pattern comprises a looping test pattern consisting of a shifting 1 bit in a field of 0 bits or a shifting 0 bit in a field of 1 bits, and wherein said means for providing said second portion of said test pattern to said logic circuitry includes a compare shift register having multiple latches and a feedback path from an end latch in the compare shift register to a first latch in the compare shift register such that shifting of said 1 bit in said field of 0 bits or said 0 bit in said field of 1 bits results in data from an end latch in the compare shift register being automatically fed back to said first latch in said compare shift register, thereby defining said looping test pattern.

Claim 7

The system of claim 3, wherein said first portion of said test pattern and said second portion of said test pattern together comprise a looping test pattern, and wherein said means for providing said first portion of said test pattern to said memory array comprises an input shift register and said means for providing said second portion of said test pattern to said logic circuitry comprises a compare shift register, said input shift register having multiple latches and said compare shift register having multiple latches, an end latch in said input shift register being electrically coupled to output data to a first latch in said compare shift register and an end latch in said compare shift register being electrically coupled back to output data to a first latch in said input shift register, wherein introduction and shifting of a 1 bit in a field of 0 bits or a 0 bit in a field of 1 bits in said input shift register and said compare shift register defines said looping test pattern, said looping test pattern providing different test patterns across said port A input and said port B input of said logic circuitry.

Claim 8

The system of claim 3, wherein said logic circuitry comprises comparator logic circuitry and wherein said test pattern comprises a deterministic test pattern.

Claim 9

The system of claim 3, further comprising circuit means for providing a pass/fail signal based upon application of said test pattern to said logic circuitry, said pass/fail signal comprising a single bit pass/fail signal.

Claim 10

The system of claim 8, wherein said circuit means for providing said pass/fail signal includes a compression/compare circuit coupled to receive an output of said logic circuitry and an expect data signal from said BIST, said compression/compare circuitry comprising means for comparing said output of said logic circuitry and said expect data from said BIST to generate said single bit pass/fail signal.

Claim 11

An integrated circuit chip comprising: a memory array for storing data, said memory array having an input port and an output port; a logic circuit electrically coupled to the output port of said memory array so that stored data read from said memory array flows via said output port to said logic circuit; and on-chip Built-In Self-Test (BIST) means for testing said logic circuit including means for generating a test pattern for testing said logic circuit, and means for providing said test pattern to said logic circuit including means for writing at least a portion thereof into said memory array and then reading said portion of said test pattern out of said memory array via said output port to said logic circuit for testing said logic circuit.

Claim 12

An integrated circuit chip comprising: a memory array for storing data, said memory array having an input port and an output port; a logic circuit electrically coupled to the output port of said memory array so that stored data read from said memory array flows via said output port to said logic circuit; and on-chip Built-In Self-Test (BIST) means for testing said logic circuit including means for generating a test pattern for testing said logic circuit, and means for providing said test pattern to said logic circuit including means for writing at least a portion thereof into said memory array and then reading said portion of said test pattern out of said memory array via said output port to said logic circuit for testing said logic circuit.

Claim 13

The integrated circuit chip of claim 10, wherein said logic circuit contains a port A input and a port B input, said port A input being electrically coupled to said output port of said memory array, and wherein said portion of said test pattern written to and read from said memory array comprises a first portion of said test pattern, and said on-chip BIST means further comprises means for providing a second portion of said test pattern to said port B input of said logic circuit without passing said second portion of said test pattern through said memory array.

Claim 14

The integrated circuit chip of claim 11, wherein said port A input and said port B input are each N-1 bits wide, N being an integer ≧2, and wherein said second portion of said test pattern comprises a looping test pattern consisting of a shifting 1 bit in a field of N-2 0 bits or a shifting 0 bit in a field of N-21 bits, and wherein said first portion of said test pattern comprises either N-1 1 bits or N-1 0 bits.

Claim 15

The integrated circuit chip of claim 11, wherein said port A input and said port B input are each N-1 bits wide, N being an integer ≧2, and wherein said first portion of said test pattern comprises a looping test pattern consisting of a shifting 1 bit in a field of 0 bits or a shifting 0 bit in a field of 1 bits, and wherein said second portion of said test pattern comprises either all 0 bits or all 1 bits.

Claim 16

The integrated circuit chip of claim 11, wherein said means for providing said second portion of said test pattern to said logic circuit includes a compare shift register electrically coupled between said means for generating said test pattern and said logic circuit, said compare shift register comprising means for presenting said second portion of said test pattern to said port B input of said logic circuit.

Claim 17

The integrated circuit chip of claim 11, wherein said means for writing said first portion of said first test pattern into said memory includes an input shift register electrically coupled between said means for generating said test pattern and said input port of said memory array, said input shift register including feedback means between an end latch in said input shift register and a first latch in said input shift register, said first portion of said test pattern comprising a looping test pattern consisting of a shifting 1 bit in a field of 0 bits or a shifting 0 bit in a field of 1 bits.

Claim 18

The integrated circuit chip of claim 11, wherein said first portion of said test pattern includes N bits, N being an integer ≧2, and wherein one bit of said N bits comprises an invalid data bit which when asserted disables operation of said logic circuit.

Claim 19

The integrated circuit chip of claim 10, wherein said integrated circuit chip comprises a microprocessor chip, said memory array comprises a directory array and said logic circuit comprises a comparator logic circuit.

Claim 22

The method of claim 18, wherein said writing step (b) comprises writing a first portion of said test pattern into said memory array, and wherein said method further comprises the step of providing a second portion of said test pattern to said logic circuitry without writing said second portion of said test pattern into said memory array.

Claim 23

The method of claim 19, wherein said first portion of said test pattern comprises all 1 bits or all 0 bits, and wherein said second portion of said test pattern comprises a looping test pattern consisting of a shifting 1 bit in a field of 0 bits or a shifting 0 bit in a field of 1 bits.

Claim 24

The method of claim 19, wherein said first portion of said test pattern comprises a looping test pattern consisting of a shifting 1 bit in a field of 0 bits or a shifting 0 bit in a field of 1 bits, and wherein said second portion of said test pattern comprises all 1 bits or all 0 bits.

Claim 25

The method of claim 18, wherein said embedded logic circuitry and memory array reside on a microprocessor chip, and wherein said method further comprises performing said steps (a)-(c) automatically upon activation of said microprocessor chip.