Patent US5550406A successfully refreshed from Google Patents.
US5550406A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-layer tab tape having distinct signal, power and ground planes and wafer probe card with multi-layer substrate
Assignee: LSI Corp
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Filing: 1993-12-20
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Granted: 1996-08-27
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Expires: 2013-12-20
Abstract
Abstract One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed. The present invention further provides a wafer probe card which includes a multi-layer, relatively flexible tape-like substrate having a first conductive layer patterned to have a number of probe leads. The first conductive layer of probe leads are formed on an insulating layer having an inner peripheral edge defining a central opening in which an IC die is placed for testing. The insulating layer further includes inner and outer peripheral openings therethrough and a second conductive layer is provided on a side of the insulating layer opposite the probe leads. Inner and outer edge portions of the second conductive layer are exposed through the inner and outer peripheral openings, respectively. Selected probe leads are cut at an edge of the inner and outer peripheral openings in the insulating layer, bent past the insulating layer and bonded to the exposed inner and outer edge portions of the second conductive layer.
Inventors
- 👤 John McCormick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:30
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07342; H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; H10W; H10W40/00; H10W40/20; H10W40/22; H10W70/00; H10W70/40; H10W70/453; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W70/688; H10W72/00; H10W72/071; H10W72/077; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W90/401; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W70/682; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/531; H10W72/5363; H10W72/541; H10W72/5449; H10W72/547; H10W72/551; H10W72/552; H10W72/5522; H10W72/581; H10W72/701; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121; Y10T29/49124; Y10T29/4913; Y10T29/49133; Y10T29/49135; Y10T29/49147; Y10T29/49151
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
181 words
A wafer probe card for testing an integrated circuit die, comprising: a first conductive layer patterned to have a plurality of probe leads, said probe leads having an inner end and an outer end; an insulating layer, having an inner peripheral edge defining a central opening in which said integrated circuit die is disposed during testing, supporting said probe leads with the inner ends of said probe leads extended in a direction toward said central opening; an inner peripheral opening in said insulating layer near said inner peripheral edge and having an inner and an outer edge; a second conductive layer provided on a side of said insulating layer opposite said probe leads and having an inner edge portion exposed within said inner peripheral opening in said insulating layer with the first conductive layer, insulating layer and second conductive layer forming a substrate; and selected probe leads cut closely adjacent to said outer edge of said inner peripheral opening in said insulating layer, bent past said insulating layer, and bonded to said exposed inner edge portion of said second conductive layer.
Claim 2
Dependent Claim
181 words
A wafer probe card for testing an integrated circuit die, comprising: a first conductive layer patterned to have a plurality of probe leads, said probe leads having an inner end and an outer end; an insulating layer, having an inner peripheral edge defining a central opening in which said integrated circuit die is disposed during testing, supporting said probe leads with the inner ends of said probe leads extended in a direction toward said central opening; an inner peripheral opening in said insulating layer near said inner peripheral edge and having an inner and an outer edge; a second conductive layer provided on a side of said insulating layer opposite said probe leads and having an inner edge portion exposed within said inner peripheral opening in said insulating layer with the first conductive layer, insulating layer and second conductive layer forming a substrate; and selected probe leads cut closely adjacent to said outer edge of said inner peripheral opening in said insulating layer, bent past said insulating layer, and bonded to said exposed inner edge portion of said second conductive layer.
Claim 3
Dependent Claim
94 words
The wafer probe card of claim 1 further comprising: an outer peripheral opening in said insulating layer near an outer peripheral edge of said insulating layer and having an inner and an outer edge; an outer edge portion of said second conductive layer extending into an area under said outer peripheral opening in said insulating layer; and said selected probe leads cut closely adjacent to said inner edge of said outer peripheral opening in said insulating layer, bent past said insulating layer, and bonded to said outer edge portion of said second conductive layer.
Claim 4
Dependent Claim
38 words
The wafer probe card of claim 1 wherein said inner peripheral opening in said insulating layer is an elongated slit substantially parallel to said inner peripheral edge of said insulating layer and substantially transverse to said probe leads.
Claim 5
Dependent Claim
38 words
The wafer probe card of claim 2 wherein said outer peripheral opening in said insulating layer is an elongated slit substantially parallel to said inner peripheral edge of said insulating layer and substantially transverse to said probe leads.
Claim 6
Dependent Claim
44 words
The wafer probe card of claim 1 wherein said inner ends of said probe leads extend within said central opening in said insulating layer such that said inner ends of said probe leads make electrical contact with said die during testing of said die.
Claim 7
Dependent Claim
49 words
The wafer probe card of claim 1 wherein a probe tip is attached to at least one of said inner ends of said probe leads such that said probe tip makes electrical contact between said inner end of said probe lead and said die during testing of said die.
Claim 8
Dependent Claim
17 words
The wafer probe card of claim 6 wherein said probe tip is constructed of a beryllium-copper alloy.
Claim 9
Dependent Claim
20 words
The wafer probe card of claim 1 wherein said second conductive layer is sufficiently thick to substantially rigidize said substrate.
Claim 10
Dependent Claim
26 words
The wafer probe card of claim 1 wherein said selected probe leads are electrically connected to said second conductive layer by a thermostatically bumpless TAB bond.
Claim 11
Dependent Claim
16 words
The wafer probe card of claim 1 wherein said second conductive layer is a ground plane.
Claim 12
Dependent Claim
16 words
The wafer probe card of claim 1 wherein said second conductive layer is a power plane.
Claim 13
Dependent Claim
146 words
The wafer probe card of claim 1 further comprising: a printed circuit board having a plurality of traces thereon and a central opening therethrough, at least one of said outer ends of said probe leads being electrically connected to at least one of said traces such that test signals from said printed circuit board may be supplied to said probe lead; and an insulating support plate attached to said printed circuit board and having a central opening therethrough within an area defined by said central opening in said printed circuit board with said second conductive layer attached to said insulating support plate on a side of said plate opposite a side attached to said printed circuit board and with said insulating layer being attached to said second conductive layer at a side of said second conductive layer opposite a side attached to said insulating support plate.
Claim 14
Dependent Claim
26 words
The wafer probe card of claim 12 wherein said inner ends of said probe leads are formed with a bend in a direction toward said die.
Claim 15
Dependent Claim
46 words
The wafer probe card of claim 13 wherein an inner periphery of said insulating support plate is shaped to maintain said bend in said inner ends of said probe leads when said inner ends are brought into contact with said die during testing of said die.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |