Error correction encoding and decoding system

Claim 2

An error correction encoding device comprising: a memory for storing information codes in a form of a data matrix having row addresses and column addresses; first correction encoding means for reading the information codes from the memory and producing a first error-correcting code word composed of the information codes extracted from the data matrix and first parity check codes generated by using the information codes, said first error correction encoding means extracting the information codes from addresses which have different column addresses and only one of every adjacent n row addresses (where n is 2 or a larger integer) on the data matrix; and second error correction encoding means for extracting the information codes from the data matrix in the row direction thereof and producing a second error-correcting code word composed of the information codes extracted from the data matrix and second parity check codes generated by using the information codes, said second error correction encoding means extracting the information codes from addresses which have the same column address on the data matrix.

Claim 3

A device according to claim 1 wherein said first error correction encoding means outputs an odd code word composed of odd parity check codes and only information codes whose row addresses are odd and an even code word composed of even parity check codes and only information codes whose row addresses are even as said first error-correcting code word.

Claim 4

A device according to claim 2 wherein said first error correction encoding means writes the odd parity check codes at only odd row addresses in the memory, and the even parity check codes at only even row addresses in the memory.

Claim 5

A device according to claim 1 wherein said first error correction encoding means writes the first parity check codes at row addresses larger than those of the information codes in the memory, and the memory reads the information codes and the first parity check codes in order of row addresses in units of a data frame including a plurality of information codes and parity check codes whose column addresses are the same.

Claim 6

A device according to claim 4 wherein said second error correction encoding means writes the second parity check codes at row addresses larger than those of the first parity check codes in the memory.

Claim 7

A code transmitting apparatus comprising: input means for inputting information codes; a memory for storing the information codes entered at said input means in a form of a data matrix having row addresses and column addresses, said memory writing the information codes sequentially every row of said data matrix; error correction encoding means for reading the information codes from the memory and producing an error-correcting code word composed of the information codes extracted from the data matrix and parity check codes generated by using the information codes, said error correction encoding means extracting the information codes from addresses which have different column addresses and only one of every adjacent n row addresses (wherein n is 2 or a larger integer) on the data matrix; and transmitting means for transmitting the information codes and the parity check codes forming the error-correcting code word produced by said error correction encoding means in units of a data frame including a plurality of information codes whose column addresses in said memory are the same.

Claim 8

A code transmitting apparatus comprising: input means for inputting information codes; a memory for storing the information codes entered at said input means in a form of a data matrix having row addresses and column addresses, said memory writing the information codes sequentially every row of said data matrix; error correction encoding means for reading the information codes from the memory and producing an error-correcting code word composed of the information codes extracted from the data matrix and parity check codes generated by using the information codes, said error correction encoding means extracting the information codes from addresses which have different column addresses and only one of every adjacent n row addresses (wherein n is 2 or a larger integer) on the data matrix; and transmitting means for transmitting the information codes and the parity check codes forming the error-correcting code word produced by said error correction encoding means in units of a data frame including a plurality of information codes whose column addresses in said memory are the same.

Claim 9

An apparatus according to claim 6 further comprising code converting means for converting said information codes into codes whose low-frequency components are suppressed by utilizing correlations among the information codes.

Claim 10

An apparatus according to claim 6, wherein said transmitting means includes a synchronism addition means for appending synchronizing code to leading ends of said data frames.

Claim 11

An apparatus according to claim 6 wherein said transmitting means includes another error correction encoding means for producing another error-correcting code word in units of the data frame.

Claim 12

An error correction code decoding device, comprising: a memory for storing first and second check codes and information codes composing first and second error-correcting code words in a form of a data matrix having row addresses and column addresses, the information codes and first check codes, composing the first error-correcting code word, being stored in addresses which have different column addresses and only one of every adjacent n row addresses on the data matrix, and the information codes and second check codes, composing the second error-correcting code word, being stored in addresses which have the same column addresses on the data matrix; second error correcting means for reading the information codes and the second check codes from the memory and correcting errors of the information codes, said second error correction means extracting the information codes from addresses which have the same column address on the data matrix; and first error correcting means for reading the information codes and the first check codes from the memory and correcting errors of the information codes, said first error correcting means extracting the information codes from addresses which have different column addresses and only of every adjacent n row addresses (where n is 2 or a larger integer) on the data matrix.

Claim 13

An error correction code decoding device, comprising: a memory for storing first and second check codes and information codes composing first and second error-correcting code words in a form of a data matrix having row addresses and column addresses, the information codes and first check codes, composing the first error-correcting code word, being stored in addresses which have different column addresses and only one of every adjacent n row addresses on the data matrix, and the information codes and second check codes, composing the second error-correcting code word, being stored in addresses which have the same column addresses on the data matrix; second error correcting means for reading the information codes and the second check codes from the memory and correcting errors of the information codes, said second error correction means extracting the information codes from addresses which have the same column address on the data matrix; and first error correcting means for reading the information codes and the first check codes from the memory and correcting errors of the information codes, said first error correcting means extracting the information codes from addresses which have different column addresses and only of every adjacent n row addresses (where n is 2 or a larger integer) on the data matrix.

Claim 14

A system device according to claim 10 wherein the first error-correcting code word includes an odd code word produced using only information codes whose row addresses are odd and an even code word produced using only information codes whose row addresses are even, and said first error correction means processes the odd code word and the even code word in parallel.

Claim 15

A code receiving apparatus, comprising: input means for inputting check codes and information codes forming an error-correcting code word; a memory for storing the check codes and the information codes input from said input means in a form of a data matrix having row addresses and column addresses, said memory writing the check codes and the information codes in units of a row of the data matrix; and error correcting means for reading the check codes and the information codes from the memory and correcting errors of the information codes, said error correcting means extracting the information codes from addresses which have different column addresses and only one of every adjacent n row addresses (where n is 2 or a larger integer) on the data matrix.

Claim 16

A code receiving apparatus, comprising: input means for inputting check codes and information codes forming an error-correcting code word; a memory for storing the check codes and the information codes input from said input means in a form of a data matrix having row addresses and column addresses, said memory writing the check codes and the information codes in units of a row of the data matrix; and error correcting means for reading the check codes and the information codes from the memory and correcting errors of the information codes, said error correcting means extracting the information codes from addresses which have different column addresses and only one of every adjacent n row addresses (where n is 2 or a larger integer) on the data matrix.