US4796261A
Expired / Lapsed
US
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Error correction apparatus for digital data
Assignee: Sony Corp
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Filing: 1987-01-22
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Granted: 1989-01-03
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Expires: 2007-01-22
Abstract
Abstract An error correcting system in which received digital data is subjected to correcting processes by first and second error correction codes alternately is provided with memories to store first and second series error pointers for a plurality of series of the first and second error correction codes, and such first and second series error pointers are read to determine which series are without error, whereupon the correcting processes of the first and second error correction codes are omitted with respect to the error-free series. As a result, the number of times effective correcting processes can be repeated within a limited time is increased and the correcting capability can be substantially improved.
Inventors
- 👤 Hisayoshi Moriwaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:23
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
172 words
An apparatus for correcting errors in received digital data signals having parity series and CRC codes, comprising: means for generating word error pointers on the basis of the CRC codes included in said received digital signals; word error pointer memory means for storing said word error pointers; means for generating series error pointers of predetermined parity series of said received digital signals; parity series error pointer memory means for storing said series error pointers; means for reading out said word error pointers of said predetermined parity series from said word error pointer memory means; counting means for determining how many of said word error pointers read from said word error pointer memory means indicate error words; means for correcting errors included in said received digital signals of said predetermined parity series when only one of said word error pointers read from said word error pointer memory means indicates an error word; and means for clearing the series error pointer for the error corrected series from said parity series error pointer memory means.
Claim 2
Independent Claim
172 words
An apparatus for correcting errors in received digital data signals having parity series and CRC codes, comprising: means for generating word error pointers on the basis of the CRC codes included in said received digital signals; word error pointer memory means for storing said word error pointers; means for generating series error pointers of predetermined parity series of said received digital signals; parity series error pointer memory means for storing said series error pointers; means for reading out said word error pointers of said predetermined parity series from said word error pointer memory means; counting means for determining how many of said word error pointers read from said word error pointer memory means indicate error words; means for correcting errors included in said received digital signals of said predetermined parity series when only one of said word error pointers read from said word error pointer memory means indicates an error word; and means for clearing the series error pointer for the error corrected series from said parity series error pointer memory means.
Claim 3
Dependent Claim
60 words
An apparatus according to claim 1; further comprising pointer discriminating means for checking the series error pointers stored in said parity series error pointer memory means, and being operative, when the checked series error pointer shows no error, to check the next series error pointer without reading out the corresponding word error pointers from said word error pointer memory means.
Claim 4
Dependent Claim
40 words
An apparatus according to claim 1; wherein all of said series error pointers in said parity series error pointer memory means are set at the beginning of an error correcting operation on a predetermined amount of said received digital data.
Claim 5
Dependent Claim
35 words
An apparatus according to claim 1; wherein said clearing means also clears the corresponding series error pointer when said counting means shows no error in the words corresponding to the read out word error pointers.
Claim 6
Independent Claim
126 words
a method for correcting errors in received digital data signals having parity series and CRC codes, comprising the steps of: generating word error pointers on the basis of the CRC codes included in said received digital signals; storing said word error pointers; generating series error pointers of predetermined parity series of the received digital signals; storing said series error pointers; reading the stored word error pointers of said predetermined parity series; determining how many of said word error pointers which are read indicate error words; correcting errors included in the received digital signals of said predetermined parity series when only one error word is indicated by the word error pointers which are read; and clearing the stored series error pointer corresponding to the error corrected series.
Claim 7
Independent Claim
126 words
a method for correcting errors in received digital data signals having parity series and CRC codes, comprising the steps of: generating word error pointers on the basis of the CRC codes included in said received digital signals; storing said word error pointers; generating series error pointers of predetermined parity series of the received digital signals; storing said series error pointers; reading the stored word error pointers of said predetermined parity series; determining how many of said word error pointers which are read indicate error words; correcting errors included in the received digital signals of said predetermined parity series when only one error word is indicated by the word error pointers which are read; and clearing the stored series error pointer corresponding to the error corrected series.
Claim 8
Dependent Claim
48 words
A method according to claim 5; further comprising the steps of checking one of the stored series error pointers and, when the checked series error pointer shows no errors in any of the corresponding words, checking the next series error pointer without reading the stored word error pointers.
Claim 9
Dependent Claim
33 words
A method according to claim 5; in which all of said series error pointers are set at the initiation of the error correcting operation on a predetermined amount of said received digital data.
Claim 10
Dependent Claim
27 words
A method according to claim 5; further comprising also clearing the corresponding series error pointer when the word error pointers which are read indicate no word errors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-03 | 1992-07-04 | 1993-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-03 | 1996-07-04 | 1997-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-03 | 2000-07-04 | 2001-01-03 | $7700.00 | Window Closed / Lapsed |