US4646170A
Expired / Lapsed
US
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Method and apparatus for recording and reproducing a digital signal with a stationary head
Assignee: Hitachi Ltd
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Filing: 1985-07-22
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Granted: 1987-02-24
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Expires: 2005-07-22
Abstract
Abstract In a stationary head type PCM recorder having an A/D converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay means for adding an error detection and correction code and a predetermined signal to the digital signal for each error correction group of a predetermined number of samples, and a multi-track head for recording an output of the signal processing circuit on a plurality of tracks of a magnetic record medium and reproducing the signals recorded on the magnetic record medium; incorrectability of the error detection and correction code for a burst error in the output analog signal due to a burst error in the reproduced output is reduced by delaying parity data by the error detection and correction code and the digital signal data by different delay times such that the digital signal data are dispersely recorded in a track direction and a tape transport direction, and allotting the delayed data to the multi-track head such that the data of the adjacent sample points are spaced from each other by at least the distribution length of the parity data and the parity data is arranged between the distributed adjacent data.
Inventors
- 👤 Masaharu Kobayashi
- 👤 Hiroo Okamoto
- 👤 Takao Arai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:16
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/09; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; G11B20/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
289 words
In a stationary multi-track head type PCM recorder having an A/D converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay and encoder means for adding parity words and a predetermined signal to said digital signal of each of a predetermined number of samples to form a frame for error detection and correction, and multi-track heads for recording an output of said signal processing circuit on a plurality of tracks of a recording tape in parallel in a tape transport direction and reproducing the signals recorded on the recording tape; a digital signal recording method for reducing incorrectability of said error detection and correction code for a burst error in the output analog signal due to a burst error in the reproduced output, comprising the steps of: delaying parity words derived from said frame for error detection and correction and said digital signal data by different delay times such that said digital signal data is distributedly recorded on said plurality of tracks in a track-width direction and the tape transport direction and the data of adjacent sample points which are consecutive in original time sequence are separated from each other into first and second groups in areas spaced in the tape transport direction in each error detection and correction frame, while said parity words are distributed in a third group in an area between the spaced first and second groups; and allotting the delayed data to said multi-track heads such that the data of said first and second group areas are located on center-side tracks of the recording tape and the parity words in said third group area are located on edge-side tracks of the recording tape.
Claim 2
Dependent Claim
289 words
In a stationary multi-track head type PCM recorder having an A/D converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay and encoder means for adding parity words and a predetermined signal to said digital signal of each of a predetermined number of samples to form a frame for error detection and correction, and multi-track heads for recording an output of said signal processing circuit on a plurality of tracks of a recording tape in parallel in a tape transport direction and reproducing the signals recorded on the recording tape; a digital signal recording method for reducing incorrectability of said error detection and correction code for a burst error in the output analog signal due to a burst error in the reproduced output, comprising the steps of: delaying parity words derived from said frame for error detection and correction and said digital signal data by different delay times such that said digital signal data is distributedly recorded on said plurality of tracks in a track-width direction and the tape transport direction and the data of adjacent sample points which are consecutive in original time sequence are separated from each other into first and second groups in areas spaced in the tape transport direction in each error detection and correction frame, while said parity words are distributed in a third group in an area between the spaced first and second groups; and allotting the delayed data to said multi-track heads such that the data of said first and second group areas are located on center-side tracks of the recording tape and the parity words in said third group area are located on edge-side tracks of the recording tape.
Claim 3
Dependent Claim
81 words
A digital signal recording method according to claim 1 wherein the analog signal is sampled from first and second channels, the sample data is spaced on the first half and the second half of the data tracks in the track-width direction, respectively, and the first channel sample data and the second channel sample data are spaced from each other in the track-length direction, and the first and second channels are spaced in the opposite relation between the distributed adjacent data groups.
Claim 4
Dependent Claim
33 words
A digital signal recording method according to claim 1 wherein the analog signal is sampled from first and second channels, and the first and second channel sample data are recorded on each track.
Claim 5
Dependent Claim
84 words
A digital signal recording method according to claim 1 wherein said digital signal data is sampled from first and second channel audio signals, and said delaying step includes a step for imparting a large delay to the correction group of one of the first and second channel sample signals such that the odd data and the even data are separated from each other in the tape transport direction by at least a total distribution length of said third group along the tape transport direction.
Claim 6
Dependent Claim
105 words
A digital signal recording method according to claim 4 wherein a first half of the even data and a second half of the odd data of the first channel, and a second half of the even data and a first half of the odd data of the second channel are recorded in the center tracks of the plurality of signal data record tracks, and the latter half of the even data and the first half of the first channel and the first half of the even data and the second half of the odd data of the second channel are recorded in the edge tracks.
Claim 7
Dependent Claim
55 words
A digital signal recording method according to claim 4 wherein said data allotting step allots the such that the even data of the first and second channels is arranged on the odd tracks and the odd data is arranged in the even tracks and the first and second channel data is included in each track.
Claim 8
Dependent Claim
17 words
The method according to claim 1, wherein said parity words are generated by using a Reed-Solomon code.
Claim 9
Dependent Claim
283 words
A stationary multi-track head type PCM recorder having and A/D converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay and encoder means for adding parity words and a predetermined signal to said digital signal of each predetermined number of samples to form a frame for error detection and correction, and multi-track heads for recording an output of said signal processing circuit on a plurality of tracks of a recording tape in parallel in a tape-transport direction and reproducing the signals recorded on the recording tape, said signal processing circuit comprising: means for delaying parity words derived from said error detection and correction frame and said digital signal data by different delay times such that said digital signal data is distributedly recorded on said plurality of tracks in the track-width direction and the tape transport direction and for separating the data of adjacent sample points which are consecutive in original time sequence into first and second groups in areas spaced in the tape transport direction in each error detection and correction frame, while said parity words are distributed in a third group in an area between the spaced first and second groups; and means for allotting the delayed data to said multi-track heads such that the data of said first and second group areas are located on center-side tracks of the recording tape and the parity words in said third group area are located on edge-side tracks of the recording tape; whereby the incorrectability of said error detection and correction code for a burst error in the output analog signal due to a burst error in a reproduced output is reduced.
Claim 10
Dependent Claim
283 words
A stationary multi-track head type PCM recorder having and A/D converter for sampling an analog signal and converting the analog signal to a digital signal, a signal processing circuit including data delay and encoder means for adding parity words and a predetermined signal to said digital signal of each predetermined number of samples to form a frame for error detection and correction, and multi-track heads for recording an output of said signal processing circuit on a plurality of tracks of a recording tape in parallel in a tape-transport direction and reproducing the signals recorded on the recording tape, said signal processing circuit comprising: means for delaying parity words derived from said error detection and correction frame and said digital signal data by different delay times such that said digital signal data is distributedly recorded on said plurality of tracks in the track-width direction and the tape transport direction and for separating the data of adjacent sample points which are consecutive in original time sequence into first and second groups in areas spaced in the tape transport direction in each error detection and correction frame, while said parity words are distributed in a third group in an area between the spaced first and second groups; and means for allotting the delayed data to said multi-track heads such that the data of said first and second group areas are located on center-side tracks of the recording tape and the parity words in said third group area are located on edge-side tracks of the recording tape; whereby the incorrectability of said error detection and correction code for a burst error in the output analog signal due to a burst error in a reproduced output is reduced.
Claim 11
Dependent Claim
23 words
A PCM recorder according to claim 8, wherein said signal processing circuit includes means for generating said parity words using a Reed-Solomon code.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |