Schilling-Manela forward error correction and detection code method and apparatus

Claim 2

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence in memory means having g rows by h columns of information-memory cells; calculating parity-check symbols from parity-line symbols having p-bits per symbol, along a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo-2 p the parity-line symbols along each of the parity lines, respectively; setting the parity-check symbol for each parity line equal to the modulo-2 p sum of the parity-line symbols along each parity line, respectively; storing the parity-check symbols in r parity-memory cells of said memory means, and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 3

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence in memory means having at least g rows by h columns of information-memory cells; calculating parity-check symbols from parity-line symbols having p bits per symbol, along at least two parity paths having different slopes in the g rows by h columns of said information-memory cells by adding modulo-2 p the parity-line symbols along each of the parity paths; and setting the parity-check symbol for each parity path equal to the modulo-2 p sum of the parity-line symbols along each of the parity paths, respectively.

Claim 4

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence in memory means having at least g rows by h columns of information-memory cells; calculating parity-check symbols from parity-line symbols having p bits per symbol, along at least two parity paths having different slopes in the g rows by h columns of said information-memory cells by adding modulo-2 p the parity-line symbols along each of the parity paths; and setting the parity-check symbol for each parity path equal to the modulo-2 p sum of the parity-line symbols along each of the parity paths, respectively.

Claim 5

The process for encoding the Schilling-Manela error correcting code as set forth in claim 1 or 2, wherein the steps of: calculating parity-check symbols from parity-line symbols includes calculating parity-check symbols from data symbols; and setting parity-check symbols for each parity line equal to the modulo-2 p sum of the parity-line symbols includes setting the parity-check symbols for each parity line equal to the modulo 2 sum of the data symbols.

Claim 6

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-bit sequence in memory means having g rows by h columns of information-memory cells; calculating parity-check bits from parity-line bits, along at least a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo 2 the parity-line bits along each of the parity lines, respectively; setting the parity-check bit for each parity line equal to the modulo 2 sum of the parity-line bits along each parity line, respectively; storing the parity-check bits in r parity-memory cells of said memory means, and outputting an encoded data-bit sequence comprising the data bit sequence and the parity-check bits.

Claim 7

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-bit sequence in memory means having g rows by h columns of information-memory cells; calculating parity-check bits from parity-line bits, along at least a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo 2 the parity-line bits along each of the parity lines, respectively; setting the parity-check bit for each parity line equal to the modulo 2 sum of the parity-line bits along each parity line, respectively; storing the parity-check bits in r parity-memory cells of said memory means, and outputting an encoded data-bit sequence comprising the data bit sequence and the parity-check bits.

Claim 8

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell; and substituting the new-data symbol into the stored data-symbol sequence.

Claim 9

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell; and substituting the new-data symbol into the stored data-symbol sequence.

Claim 10

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; and inverting, provided the largest number exceeds, the threshold, the data symbol in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

Claim 11

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; and inverting, provided the largest number exceeds, the threshold, the data symbol in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

Claim 12

The process for decoding a Schilling-Manela error correcting and detecting code as set forth in claim 6, further comprising the steps of: repeating the steps of finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell; until the largest number does not exceed the threshold, thereby determining all of the composite cells exceeding a threshold, and testing one at a time by inverting the bit in that composite cell exceeding the threshold and determining a new composite-error graph for each subsequent cell inversion.

Claim 13

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check bit and the parity-line bits along a first parity line in the g rows by h columns of information memory cells, having an error; finding the parity-check bit and the parity-line bits along a second parity line in the g rows by h columns of information memory cells, having an error; inverting the data bit at the intersection of the first and second parity lines; and outputting the corrected data-bit sequence.

Claim 14

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check bit and the parity-line bits along a first parity line in the g rows by h columns of information memory cells, having an error; finding the parity-check bit and the parity-line bits along a second parity line in the g rows by h columns of information memory cells, having an error; inverting the data bit at the intersection of the first and second parity lines; and outputting the corrected data-bit sequence.

Claim 15

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-symbol sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check symbol and parity-line symbols along a first parity line in the g rows by h columns of information memory cells, having an error; finding the parity-check symbol and parity-line symbols along a second parity line in the g rows by h columns of information memory cells, having an error; comparing the parity-check symbols and parity-line symbols along the first and second parity lines, respectively, for determining the parity-line symbol having an error; substituting a new-parity-line symbol for the parity-line symbol having an error so that first and second parity lines are not in error; and outputting the corrected data-symbol sequence.

Claim 16

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-symbol sequence in memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check symbol and parity-line symbols along a first parity line in the g rows by h columns of information memory cells, having an error; finding the parity-check symbol and parity-line symbols along a second parity line in the g rows by h columns of information memory cells, having an error; comparing the parity-check symbols and parity-line symbols along the first and second parity lines, respectively, for determining the parity-line symbol having an error; substituting a new-parity-line symbol for the parity-line symbol having an error so that first and second parity lines are not in error; and outputting the corrected data-symbol sequence.

Claim 17

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-symbol sequence; and processor means coupled to said memory means for calculating parity-check symbols from parity-line symbols having p-bits per symbol, along a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo-2 p the parity-line symbols along each of the parity lines, respectively, and setting the parity-check symbol for each parity line equal to the modulo-2 p sum of the parity-line symbols along each parity line, respectively, and storing the parity-check symbols in the r parity-memory cells of said memory means, and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 18

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-symbol sequence; and processor means coupled to said memory means for calculating parity-check symbols from parity-line symbols having p-bits per symbol, along a first and a second set of parity lines, each of the first set of parity lines having a straight diagonal path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a straight diagonal path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo-2 p the parity-line symbols along each of the parity lines, respectively, and setting the parity-check symbol for each parity line equal to the modulo-2 p sum of the parity-line symbols along each parity line, respectively, and storing the parity-check symbols in the r parity-memory cells of said memory means, and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 19

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-symbol sequence; and processor means coupled to said memory means for calculating a plurality of parity-check symbols from parity-line symbols having p bits per symbol, along a plurality of parity paths in the g rows by h columns of said information-memory cells by adding modulo-2 p the parity-line symbols along each of the parity paths, and setting the parity-check symbol for each parity path equal to the modulo-2 p sum of the parity-line symbols along each of the parity paths, respectively.

Claim 20

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-symbol sequence; and processor means coupled to said memory means for calculating a plurality of parity-check symbols from parity-line symbols having p bits per symbol, along a plurality of parity paths in the g rows by h columns of said information-memory cells by adding modulo-2 p the parity-line symbols along each of the parity paths, and setting the parity-check symbol for each parity path equal to the modulo-2 p sum of the parity-line symbols along each of the parity paths, respectively.

Claim 21

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-bit sequence; and processor means coupled to said memory means for calculating parity-check bits from parity-line bits, along a first and a second set of parity lines, each of the first set of parity lines having a path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo 2 the parity-line bits along each of the parity lines, respectively, setting the parity-check bit for each parity line equal to the modulo 2 sum of the parity-line bits along each parity line, respectively, storing the parity-check bits in r parity-memory cells of said memory means, and outputting an encoded data-bit sequence comprising the data bit sequence and the parity-check bits.

Claim 22

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means having g rows by h columns of information-memory cells and r parity-memory cells coupled to a data source for storing a block of a data-bit sequence; and processor means coupled to said memory means for calculating parity-check bits from parity-line bits, along a first and a second set of parity lines, each of the first set of parity lines having a path with a first slope through the g rows by h columns of said information-memory cells and each of the second set of parity lines having a path with a second slope through the g rows by h columns of said information-memory cells, by adding modulo 2 the parity-line bits along each of the parity lines, respectively, setting the parity-check bit for each parity line equal to the modulo 2 sum of the parity-line bits along each parity line, respectively, storing the parity-check bits in r parity-memory cells of said memory means, and outputting an encoded data-bit sequence comprising the data bit sequence and the parity-check bits.

Claim 23

The Schilling-Manela encoding apparatus as set forth in claim 10 or 12 wherein said processor means calculates parity-check bits along the first set of parity lines having the first diagonal path with a 45° slope and along the second set of parity lines having the second diagonal path with a -45° slope.

Claim 24

The Schilling-Manela encoding apparatus as set forth in claim 11 wherein said processor means further includes calculating parity-check bits from data bits along a plurality of independently sloped parity lines in which the slopes may be all positive, all negative or employ some positive and some negative slopes.

Claim 25

A Schilling-Manela decoding apparatus comprising: memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-symbol sequence, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check bits stored in the r parity-memory cells and a data-symbol sequence having information symbols stored in the g rows by h columns of said information-memory cells; a composite-error graph having g rows by h columns of composite cells; and processor means coupled to said memory means and said composite-error graph for finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error, incrementing the count of each composite cell on the composite-error graph traversed by the path of each of the parity lines having an error, determining the largest-number cell in the composite-error graph having the largest number, comparing the largest number to a threshold, determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell, and substituting the new-data symbol into the information-memory cells.

Claim 26

A Schilling-Manela decoding apparatus comprising: memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-symbol sequence, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check bits stored in the r parity-memory cells and a data-symbol sequence having information symbols stored in the g rows by h columns of said information-memory cells; a composite-error graph having g rows by h columns of composite cells; and processor means coupled to said memory means and said composite-error graph for finding the parity-check symbols and the parity-line symbols along the parity lines in the g rows by h columns of information-memory cells, having an error, incrementing the count of each composite cell on the composite-error graph traversed by the path of each of the parity lines having an error, determining the largest-number cell in the composite-error graph having the largest number, comparing the largest number to a threshold, determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell, and substituting the new-data symbol into the information-memory cells.

Claim 27

A Schilling-Manela decoding apparatus comprising: memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-bit sequence, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells and a data-bit sequence having information bits stored in the g rows by h columns of said information-memory cells; a composite-error graph having g rows by h columns of composite cells; and processor means coupled to said memory means and said composite-error graph for finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error, incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error, determining the largest-number cell in the composite-error graph having the largest number, comparing the largest number to a threshold, and inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

Claim 28

A Schilling-Manela decoding apparatus comprising: memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-bit sequence, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells and a data-bit sequence having information bits stored in the g rows by h columns of said information-memory cells; a composite-error graph having g rows by h columns of composite cells; and processor means coupled to said memory means and said composite-error graph for finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error, incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error, determining the largest-number cell in the composite-error graph having the largest number, comparing the largest number to a threshold, and inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

Claim 29

A Schilling-Manela decoding apparatus comprising: memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-bit sequence, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells and a data-bit sequence having information bits stored in the g rows by h columns of said information-memory cells; a composite-error graph having g rows by h columns of composite cells; and processor means coupled to said memory means and said composite-error graph for finding the parity-check bit and the parity-line bits along a first parity line in the g rows by h columns of information memory cells, having an error, finding the parity-check bit and the parity-line bits along a second parity line in the g rows by h columns of information memory cells, having an error, inverting the data bit at the intersection of the first and second parity lines, and outputting the corrected data-bit sequence.

Claim 30

A Schilling-Manela decoding apparatus comprising: memory means having at least g rows and h columns of information-memory cells and r parity-memory cells, coupled to a data source for storing a block of an encoded-data-bit sequence, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells and a data-bit sequence having information bits stored in the g rows by h columns of said information-memory cells; a composite-error graph having g rows by h columns of composite cells; and processor means coupled to said memory means and said composite-error graph for finding the parity-check bit and the parity-line bits along a first parity line in the g rows by h columns of information memory cells, having an error, finding the parity-check bit and the parity-line bits along a second parity line in the g rows by h columns of information memory cells, having an error, inverting the data bit at the intersection of the first and second parity lines, and outputting the corrected data-bit sequence.

Claim 31

A process for communicating in an ARQ system with the Schilling-Manela FEC and detection code comprising the steps of: storing a block of a data-symbol sequence in transmit-memory means having at least g rows by h columns of information-memory cells; calculating parity-check symbols from parity-line symbols having p bits per symbol, along at least two parity paths having different slopes in the g rows by h columns of said information-memory cells by adding modulo-2 p the parity-line symbols along each of the parity paths; setting the parity-check symbol for each parity path equal to the modulo-2 p sum of the parity-line symbols along each of the parity paths, respectively; transmitting an encoded-data-symbol sequence over a communications channel having a feedback channel, wherein said encoded-data-symbol sequence includes the parity-check-symbol sequence and the data-symbol sequence; storing the encoded-data-symbol sequence in receiver-memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell; sending a retransmit request to the transmitter if some errors are not correctable; generating a second set of parity-check symbols from the data-bit sequence stored in the transmit memory means; sending the second set of parity-check symbols over the communications channel; and using the second set of parity-check symbols, repeating the steps of finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

Claim 32

A process for communicating in an ARQ system with the Schilling-Manela FEC and detection code comprising the steps of: storing a block of a data-symbol sequence in transmit-memory means having at least g rows by h columns of information-memory cells; calculating parity-check symbols from parity-line symbols having p bits per symbol, along at least two parity paths having different slopes in the g rows by h columns of said information-memory cells by adding modulo-2 p the parity-line symbols along each of the parity paths; setting the parity-check symbol for each parity path equal to the modulo-2 p sum of the parity-line symbols along each of the parity paths, respectively; transmitting an encoded-data-symbol sequence over a communications channel having a feedback channel, wherein said encoded-data-symbol sequence includes the parity-check-symbol sequence and the data-symbol sequence; storing the encoded-data-symbol sequence in receiver-memory means having at least g rows by h columns of information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the g rows by h columns of information-memory cells; finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell; sending a retransmit request to the transmitter if some errors are not correctable; generating a second set of parity-check symbols from the data-bit sequence stored in the transmit memory means; sending the second set of parity-check symbols over the communications channel; and using the second set of parity-check symbols, repeating the steps of finding the parity-check bits and the parity-line bits along the parity lines in the g rows by h columns of information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; inverting, provided the largest number exceeds the threshold, the data bit in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, thereby the new-data symbol minimizes the count in the largest-number cell.

Claim 33

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having λ-dimensional information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the λ-dimensional information-memory cells; finding the parity-check symbols and the parity-line symbols along the parity lines in the information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell; and substituting the new-data symbol into the stored data-symbol sequence.

Claim 34

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having λ-dimensional information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence blocked and stored in the λ-dimensional information-memory cells; finding the parity-check symbols and the parity-line symbols along the parity lines in the information-memory cells, having an error; incrementing the count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error; determining the largest-number cell in the composite-error graph having the largest number; comparing the largest number to a threshold; determining, provided the largest number exceeds the threshold, a new-data symbol for the memory cell in the information-memory cells corresponding to the largest-number cell in the composite-error graph having the largest number, wherein the new-data symbol minimizes the count in the largest-number cell; and substituting the new-data symbol into the stored data-symbol sequence.

Claim 35

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-symbol sequence in memory means having λ-dimensional information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the λ-dimensional information-memory cells; finding the parity-check symbol and parity-line symbols along a first parity line in the information memory cells, having an error; finding the parity-check symbol and parity-line symbols along a second parity line in the information memory cells, having an error; comparing the parity-check symbols and parity-line symbols along the first and second parity lines, respectively, for determining the parity-line symbol having an error; substituting a new-parity-line symbol for the parity-line symbol having an error so that first and second parity lines are not in error; and outputting the corrected data-symbol sequence.

Claim 36

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-symbol sequence in memory means having λ-dimensional information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the λ-dimensional information-memory cells; finding the parity-check symbol and parity-line symbols along a first parity line in the information memory cells, having an error; finding the parity-check symbol and parity-line symbols along a second parity line in the information memory cells, having an error; comparing the parity-check symbols and parity-line symbols along the first and second parity lines, respectively, for determining the parity-line symbol having an error; substituting a new-parity-line symbol for the parity-line symbol having an error so that first and second parity lines are not in error; and outputting the corrected data-symbol sequence.

Claim 37

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence having information bits blocked and stored in the information-memory cells; finding the parity-check bit and parity-line bits along a first parity line in the information memory cells, having an erasure; and setting the erasure equal to the modulo 2 sum of the parity check bits plus the parity lines bits along the parity line.

Claim 38

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-bit sequence in memory means having information-memory cells and r parity-memory cells, wherein said encoded-data-bit sequence includes a parity-check-bit sequence having r parity-check bits stored in the r parity-memory cells, and a data-bit sequence having information bits blocked and stored in the information-memory cells; finding the parity-check bit and parity-line bits along a first parity line in the information memory cells, having an erasure; and setting the erasure equal to the modulo 2 sum of the parity check bits plus the parity lines bits along the parity line.

Claim 39

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-symbol sequence in memory means having information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the information-memory cells; finding the parity-check symbol and parity-line symbols along a first parity line in the information memory cells, having an erasure; and setting the erasure equal to the modulo 2 p sum of the parity check symbols plus the parity lines symbols along the parity line.

Claim 40

A process for decoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing an encoded-data-symbol sequence in memory means having information-memory cells and r parity-memory cells, wherein said encoded-data-symbol sequence includes a parity-check-symbol sequence having r parity-check symbols stored in the r parity-memory cells, and a data-symbol sequence having information symbols blocked and stored in the information-memory cells; finding the parity-check symbol and parity-line symbols along a first parity line in the information memory cells, having an erasure; and setting the erasure equal to the modulo 2 p sum of the parity check symbols plus the parity lines symbols along the parity line.

Claim 41

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, by setting the parity-check symbol for each of the first set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells; calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, by setting the parity-check symbol for each of the second set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 42

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, by setting the parity-check symbol for each of the first set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells; calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, by setting the parity-check symbol for each of the second set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 43

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with P-bits pre symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, by setting the parity-check symbol for each of the first set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells; calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, by setting the parity-check symbol for each of the second set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells; calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, by setting the parity-check symbol for each of the third set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells, and said third set of parity-check symbols form a third parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 44

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with P-bits pre symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, by setting the parity-check symbol for each of the first set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells; calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, by setting the parity-check symbol for each of the second set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells; calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, by setting the parity-check symbol for each of the third set of parity-check symbols for each parity line equal to the modulo-2 p sum of the data symbols along each parity line, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells, and said third set of parity-check symbols form a third parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 45

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has path with a second slope traversing through said information-memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 46

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has path with a second slope traversing through said information-memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 47

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells; calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 48

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells; calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 49

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; storing said first set of parity-check symbols in a first parity row located in said parity-check memory cells; calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells; storing said second set of parity-check symbols in a second parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 50

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; storing said first set of parity-check symbols in a first parity row located in said parity-check memory cells; calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells; storing said second set of parity-check symbols in a second parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 51

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; storing said first set of parity-check symbols in a first parity row located in said parity-check memory cells; calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells; storing said second set of parity-check symbols in a second parity row located in said parity-check memory cells; calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells; storing said third set of parity-check symbols in a third parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 52

A process for encoding a Schilling-Manela error correcting and detecting code comprising the steps of: storing a block of a data-symbol sequence having data symbols with p-bits per symbol, in memory means having information-memory cells and parity-check memory cells; calculating a first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells; storing said first set of parity-check symbols in a first parity row located in said parity-check memory cells; calculating a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells; storing said second set of parity-check symbols in a second parity row located in said parity-check memory cells; calculating at least a third set of parity-check symbols from the data symbols along a third set of parity lines, wherein each parity line of the third set of parity lines has a path with a third slope traversing through said information-memory cells; storing said third set of parity-check symbols in a third parity row located in said parity-check memory cells; and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 53

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means coupled to a data source for storing a block of a data-symbol sequence; and processor means coupled to said memory means for calculating first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells, calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells, and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.

Claim 54

A Schilling-Manela error correcting and detecting code encoding apparatus comprising: memory means coupled to a data source for storing a block of a data-symbol sequence; and processor means coupled to said memory means for calculating first set of parity-check symbols from the data symbols along a first set of parity lines, wherein each parity line of the first set of parity lines has a path with a first slope traversing through said information-memory cells, and said first set of parity-check symbols forms a first parity row located in said parity-check memory cells, calculating at least a second set of parity-check symbols from the data symbols along a second set of parity lines, wherein each parity line of the second set of parity lines has a path with a second slope traversing through said information-memory cells, and said second set of parity-check symbols form a second parity row located in said parity-check memory cells, and outputting an encoded-data-symbol sequence comprising the data-symbol sequence and the parity-check symbols.