Method of transmitting digital data in which error detection codes are dispersed using alternate delay times

Claim 1

A method of transmitting data blocks each consisting of thirty-two digital data elements as frames of one hundred and twenty-eight blocks, in which each frame also includes first and second check codes capable of detecting and correcting errors from different combinations of digital data in the blocks of the frame, said method comprising the steps of: storing, in a memory having a plurality of block storage areas, thirty-two digital data elements in each block storage area of said memory in the order of generation of said digital data elements; generating a plurality of sets of second check codes from the digital data stored in the memory in such a manner that each set of the second check codes is generated from thirty-two digital data elements existing alternately at delay block distances between successive elements of three and four blocks in the memory, and storing the second check codes in the memory at positions such that a delay block distance between adjacent second check codes included in each set is alternately three and four blocks; generating a plurality of sets of first check codes in such a manner that each set of said first check codes is generated from said digital data elements and the second check codes of a respective block storage area in the memory, and storing the second check codes in the memory; reading out from the memory and transmitting the digital data elements and the first and second check codes in the order of the block storage areas in the memory.

Claim 2

A method of transmitting data blocks each consisting of thirty-two digital data elements as frames of one hundred and twenty-eight blocks, in which each frame also includes first and second check codes capable of detecting and correcting errors from different combinations of digital data in the blocks of the frame, said method comprising the steps of: storing, in a memory having a plurality of block storage areas, thirty-two digital data elements in each block storage area of said memory in the order of generation of said digital data elements; generating a plurality of sets of second check codes from the digital data stored in the memory in such a manner that each set of the second check codes is generated from thirty-two digital data elements existing alternately at delay block distances between successive elements of three and four blocks in the memory, and storing the second check codes in the memory at positions such that a delay block distance between adjacent second check codes included in each set is alternately three and four blocks; generating a plurality of sets of first check codes in such a manner that each set of said first check codes is generated from said digital data elements and the second check codes of a respective block storage area in the memory, and storing the second check codes in the memory; reading out from the memory and transmitting the digital data elements and the first and second check codes in the order of the block storage areas in the memory.