EP0357461A2
Expired / Lapsed
EP
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Error correction circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1989-09-01
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Granted: —
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Expires: 2009-09-01
Abstract
Abstract Reed-Solomon outer code for error correction concatenated with a CRC inner code for detection of miscorrections. The error correction circuit has a parallel circuit of an RS coding sequence circuit 23 and a CRC coding sequence circuit 22 to form a sequence circuit and a control circuit 24 for selecting either one of them depending on the desired operation mode. High speed decoding is obtained since the CRC computation is carried out in parallel with the Reed-Solomon decoding operation.
Inventors
- 👤 Hideo C/O Mitsubishi Denki K.K. Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 18:08
CPC Classifications
G; G03; G03G; G03G15/00; H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H03M13/13; H03M13/15; H03M13/29
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
190 words
An error correction circuit comprising: a buffer memory for storing a plurality of interleaved data streams, each having as an external code an RS code for correcting an error in data and as an internal code a CRC for detecting an error in data; an interface for untying said interleaved data streams; a Galois field operation circuit for carrying out the four rules of arithmetic in a Galois field on a syndrome of said RS code and determining an error value based on an error location for effecting correction; an RS code sequence circuit for computing said syndrome to find an error location from results of said four rules of arithmetic operation by a Chien search; a CRC coding sequence circuit for coding and computing said CRC, said RS code sequence circuit and said CRC coding sequence circuit being paralleled to form a sequence circuit; and a control circuit for controlling said interface, said Galois field operation circuit, said RS code sequence circuit, and said CRC coding sequence circuit and outputting a control signal for selecting either said RS code sequence circuit or said CRC coding sequence circuit for operation.
Claim 2
Dependent Claim
190 words
An error correction circuit comprising: a buffer memory for storing a plurality of interleaved data streams, each having as an external code an RS code for correcting an error in data and as an internal code a CRC for detecting an error in data; an interface for untying said interleaved data streams; a Galois field operation circuit for carrying out the four rules of arithmetic in a Galois field on a syndrome of said RS code and determining an error value based on an error location for effecting correction; an RS code sequence circuit for computing said syndrome to find an error location from results of said four rules of arithmetic operation by a Chien search; a CRC coding sequence circuit for coding and computing said CRC, said RS code sequence circuit and said CRC coding sequence circuit being paralleled to form a sequence circuit; and a control circuit for controlling said interface, said Galois field operation circuit, said RS code sequence circuit, and said CRC coding sequence circuit and outputting a control signal for selecting either said RS code sequence circuit or said CRC coding sequence circuit for operation.
Claim 3
Dependent Claim
137 words
The error correction circuit of claim 1, wherein said CRC coding sequence circuit determines a first CRC check symbol of a first code stream in said interleaved code streams, which is stored in said Galois field operation circuit; said CRC coding sequence circuit determines a second CRC check symbol of a second code stream, which is logically added to said first CRC check symbol and stored; and means for carrying out repeated operations similar to that of said second code stream for the number of times equal to that of interleaving stages and, in coding, writing a resulting CRC check symbol in said Galois operation circuit in a CRC check symbol portion of said buffer memory while, in decoding, comparing said CRC check symbol with a CRC check code in said buffer memory for detecting an error.
Claim 4
Dependent Claim
44 words
The error correction circuit of claim 1 or 2, wherein, in coding, said CRC coding sequence circuit computes said CRC check symbol including said CRC check code portion in said buffer memory after said CRC check code portion in said buffer memory is cleared.
Claim 5
Dependent Claim
116 words
The error correction circuit of claim 1 or 2, wherein, in decoding, said CRC coding sequence circuit is selected to compute said CRC check symbol of said first code stream while said RS sequence circuit is not used during decoding RS codes in said second code stream but data of said first code stream in said buffer memory is corrected by RS decoding and similarly compute CRC check symbols of a code stream corrected by previous RS decoding during RS decoding of each code stream; a resulting CRC check symbol of each said code stream being logically added and compared with said CRC check code in said buffer memory to detect an error after RS decoding.
Claim 6
Dependent Claim
94 words
The error correction circuit of claim 1 or 2, wherein, in decoding, said CRC coding sequence circuit computes said CRC check symbol including said CRC check code portion of said buffer memory; said Galois operation circuit computes a CRC check symbol on said CRC check code portion of said buffer memory and logically adds a result to said CRC check symbol to eliminate any influence of said CRC check code on said CRC check symbol; said CRC check symbol being compared with said CRC check code in the buffer memory to detect an error.
References Cited (Backward Citations)
No citation records indexed.
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