Electrostatic discharge protection circuit employing a mosfet device

Claim 2

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; and active device means for variably controlling a bias voltage at said gate of said first P-FET.

Claim 3

An electrostatic discharge protection device according to claim 1 further comprising second active device means for controlling a bias voltage of the n-well body of said first P-FET.

Claim 4

An electrostatic discharge protection device according to claim 1, wherein said control means includes means for biasing the gate and the n-well body of said first P-FET to a voltage equal to a given voltage potential of said supply node when said input receives an input voltage less than said given voltage potential, and the gate to a voltage equal to said input voltage when said input voltage is greater than said given voltage potential of said supply node.

Claim 5

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; and active device means for controlling a bias voltage at said gate of said first P-FET wherein said active device means includes a second P-FET having its gate tied to said input, its source tied to said supply node and its body and drain coupled to the n-well body of said first P-FET.

Claim 6

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; and active device means for controlling a bias voltage at said gate of said first P-FET wherein said active device means includes a second P-FET having its gate tied to said input, its source tied to said supply node and its body and drain coupled to the n-well body of said first P-FET.

Claim 7

An electrostatic discharge protection device according to claim 4 wherein said control means further comprises third and fourth P-FET's and an N-FET: a drain and a gate of said N-FET, a gate of said third P-FET and a source of said fourth P-FET being coupled to said supply node; a drain of said fourth P-FET being coupled to a drain of said third P-FET, a source of said N-FET and the gate of said first P-FET; bodies of both said third and said fourth P-FET's being coupled to the n-well body of said first P-FET; and a source of said third P-FET being coupled to said input and a gate of said fourth P-FET.

Claim 8

A electrostatic discharge protection device according to claim 4 wherein said control means further comprises third and fourth P-FETs; a source of said fourth P-FET and a gate of said third P-FET being coupled to said supply node; a drain of said third P-FET and a drain of said fourth P-FET being coupled to the gate of said first P-FET; a source of said third P-FET and a gate of said fourth P-FET being coupled to said input: and a body of said third P-FET and a body of said fourth P-FET being coupled to the n-well body of said first P-FET.

Claim 9

An electrostatic discharge protection device according to claim 1 wherein a length of a channel of said first P-FET is set in accordance with a desired voltage breakdown characteristic for said functional lateral PNP bipolar transistor.

Claim 10

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit, wherein said supply node includes A.C. coupling to ground; and means for controlling a bias voltage at said gate of said first P-FET.

Claim 11

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit, wherein said supply node includes A.C. coupling to ground; and means for controlling a bias voltage at said gate of said first P-FET.

Claim 12

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; and means liar controlling a bias voltage at said gate of said first P-FET, said means for controlling including a second FET having its channel disposed serially between said gate of said first P-FET and said supply node.

Claim 13

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; and means liar controlling a bias voltage at said gate of said first P-FET, said means for controlling including a second FET having its channel disposed serially between said gate of said first P-FET and said supply node.

Claim 14

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; means for controlling a bias voltage at said gate of said first P-FET; and second means for controlling a bias voltage of the n-well body of said first P-FET, said second means comprising a second FET having its channel disposed serially between the n-well body of said first P-FET and said supply node.

Claim 15

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; means for controlling a bias voltage at said gate of said first P-FET; and second means for controlling a bias voltage of the n-well body of said first P-FET, said second means comprising a second FET having its channel disposed serially between the n-well body of said first P-FET and said supply node.

Claim 16

An electrostatic discharge protection device for a mixed voltage interface to an input of a receiving circuit that receives a logic signal having an upper state voltage potential exceeding an upper supply voltage of said receiving circuit, said electrostatic discharge protection device comprising: a P-FET, as a lateral PNP bipolar transistor, having its channel disposed electrically serially between said input and said upper supply voltage of said receiving circuit; and first control means for controlling a bias voltage at a gate of said P-FET, said first control means comprising an active device which variably controls the bias voltage at the gate of said P-FET.

Claim 17

An electrostatic discharge protection device for a mixed voltage interface to an input of a receiving circuit that receives a logic signal having an upper state voltage potential exceeding an upper supply voltage of said receiving circuit, said electrostatic discharge protection device comprising: a P-FET, as a lateral PNP bipolar transistor, having its channel disposed electrically serially between said input and said upper supply voltage of said receiving circuit; and first control means for controlling a bias voltage at a gate of said P-FET, said first control means comprising an active device which variably controls the bias voltage at the gate of said P-FET.

Claim 18

An electrostatic discharge protection device according to claim 11 further comprising second control means for controlling a bias voltage at a body of said P-FET.

Claim 19

An electrostatic discharge protection device for a mixed voltage interface to an input of a receiving circuit that receives a logic signal having an upper state voltage potential exceeding an upper supply voltage of said receiving circuit, said electrostatic discharge protection device comprising: a P-FET, as a lateral PNP bipolar transistor, having its channel disposed electrically serially between the input and the upper supply voltage of said receiving circuit; and first control means for controlling a bias voltage at a gate of said P-FET, wherein said first control means includes a first FET device having its channel disposed electrically serially between said upper supply voltage of said receiving circuit and said gate of said P-FET.

Claim 20

An electrostatic discharge protection device for a mixed voltage interface to an input of a receiving circuit that receives a logic signal having an upper state voltage potential exceeding an upper supply voltage of said receiving circuit, said electrostatic discharge protection device comprising: a P-FET, as a lateral PNP bipolar transistor, having its channel disposed electrically serially between the input and the upper supply voltage of said receiving circuit; and first control means for controlling a bias voltage at a gate of said P-FET, wherein said first control means includes a first FET device having its channel disposed electrically serially between said upper supply voltage of said receiving circuit and said gate of said P-FET.

Claim 21

An electrostatic discharge protection device according to claim 13 wherein said second control means includes a second FET device having its channel disposed electrically serially between said upper supply voltage of said receiving circuit and said body of said P-FET.

Claim 22

An electrostatic discharge protection device according to claim 14 wherein a gate of said second FET device is coupled to said input.

Claim 23

An electrostatic discharge protection device for a mixed voltage interface to an input of a receiving circuit that receives a logic signal having an upper state voltage potential exceeding an upper supply voltage of said receiving circuit, said electrostatic discharge protection device comprising: a P-FET, as a lateral PNP bipolar transistor, having its channel disposed electrically serially between said input and said upper supply voltage of said receiving circuit; and first control means for controlling a bias voltage at a gate of said P-FET, wherein said first control means includes a first FET device having its channel disposed electrically serially between said upper supply voltage of said receiving circuit and said gate of said P-FET.

Claim 24

An electrostatic discharge protection device for a mixed voltage interface to an input of a receiving circuit that receives a logic signal having an upper state voltage potential exceeding an upper supply voltage of said receiving circuit, said electrostatic discharge protection device comprising: a P-FET, as a lateral PNP bipolar transistor, having its channel disposed electrically serially between said input and said upper supply voltage of said receiving circuit; and first control means for controlling a bias voltage at a gate of said P-FET, wherein said first control means includes a first FET device having its channel disposed electrically serially between said upper supply voltage of said receiving circuit and said gate of said P-FET.

Claim 25

An electrostatic discharge protection device according to claim 16 wherein said first control means further comprises a second FET device having its channel disposed between said input and said gate of said P-FET.

Claim 26

An electrostatic discharge protection device according to claim 17 wherein a gate of said second FET device is coupled to said upper supply voltage of said receiving circuit.

Claim 27

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; and means for controlling a bias voltage at said gate of said first P-FET, said bias voltage provided by said means for controlling comprising an active voltage which is variably controlled by said means for controlling.

Claim 28

An electrostatic discharge protection device for an input of a circuit comprising: a first P-FET having an n-well body including first and second P+ implants, and a gate, wherein said n-well with said first and second P+ implants provides a functional lateral PNP bipolar transistor coupled with said first P+ implant as an emitter and said second P+ implant as a collector thereof between said input and a supply node of said circuit; and means for controlling a bias voltage at said gate of said first P-FET, said bias voltage provided by said means for controlling comprising an active voltage which is variably controlled by said means for controlling.